mwojcik
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97dfa07bdb
|
determined probable sys_clk_freq for GTX transcvr
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2021-08-06 10:05:04 +02:00 |
mwojcik
|
b2dd68bd92
|
removed unnecessary and wrong add_drtio
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2021-08-03 09:52:50 +02:00 |
mwojcik
|
cafbe97e47
|
zc706: added targets to default.nix, fixed wrong base cls
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2021-07-30 15:14:40 +02:00 |
mwojcik
|
0ce86317c9
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zc706: added rough master/satellite drtio support
|
2021-07-29 15:38:23 +02:00 |
Sebastien Bourdeauducq
|
506c741238
|
support absence of gateware RTIO clock selection mux
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2021-02-15 21:41:30 +08:00 |
Sebastien Bourdeauducq
|
1e20259c36
|
fix acpki selection
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2020-08-04 13:26:45 +08:00 |
Sebastien Bourdeauducq
|
f8d4036451
|
add ACP kernel initiator
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55
Work-in-progress, only gateware part and build system, untested.
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2020-08-04 13:15:26 +08:00 |
Sebastien Bourdeauducq
|
523524c319
|
zc706: add RTIO log channels
|
2020-07-19 14:05:35 +08:00 |
Sebastien Bourdeauducq
|
f69e41af5e
|
gateware: fix VADJ I/O standard conflict
|
2020-07-16 17:58:31 +08:00 |
Sebastien Bourdeauducq
|
6a361893c2
|
gateware: make LEDs common to all variants
Makes quick testing easier.
|
2020-07-16 17:36:27 +08:00 |
Sebastien Bourdeauducq
|
8e758ecc17
|
add RTIO analyzer core (untested)
|
2020-07-15 23:06:34 +08:00 |
Sebastien Bourdeauducq
|
a7073edf79
|
add DMA core (untested)
|
2020-07-13 10:37:17 +08:00 |
Sebastien Bourdeauducq
|
e3ff21b1b5
|
create gateware folder
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2020-07-11 17:49:54 +08:00 |