stevefan1999
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

sram: support for different burst settings on read

This commit is contained in:
mwojcik 2021-08-16 11:51:50 +02:00
parent b6dd5bea68
commit f015d6732b
1 changed files with 14 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/gateware/aux_controller.py
View File

@ -34,13 +34,8 @@ class SRAM(Module):
### ###
# probably will get removed
self.addr_base = CSRStorage(32)
# Dout : Data received from CPU, output by SRAM <- port.dat_r # Dout : Data received from CPU, output by SRAM <- port.dat_r
# Din : Data driven into SRAM, written into CPU <- port.dat_w # Din : Data driven into SRAM, written into CPU <- port.dat_w
# When stb assert, index shows word being read/written, dout/din holds <- will be removed
# data
# #
# Cycle: # Cycle:
# Then out_burst_len words are strobed out of dout # Then out_burst_len words are strobed out of dout
@ -51,20 +46,17 @@ class SRAM(Module):
self.dout = Signal(64) self.dout = Signal(64)
self.din = Signal(64) self.din = Signal(64)
# probably not correct here
self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus) ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
### Read ### Read
self.comb += [ self.comb += [
port.adr.eq(ar.addr), port.adr.eq(ar.addr), # still not sure if legal hm
r.data.eq(port.dat_r), r.data.eq(port.dat_r),
r.ready.eq(1), # r.ready.eq(1),
ar.burst.eq(axi.Burst.incr.value), # ar.burst.eq(axi.Burst.incr.value),
ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...) # ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits # ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
ar.cache.eq(0xf), # ar.cache.eq(0xf),
] ]
# read control # read control
@ -77,6 +69,7 @@ class SRAM(Module):
) )
read_fsm.act("READ_START", read_fsm.act("READ_START",
r.data.eq(port.dat_r), r.data.eq(port.dat_r),
r.resp.eq(axi.Response.okay.value),
r.valid.eq(1), r.valid.eq(1),
If(r.ready, If(r.ready,
r.data.eq(port.dat_r), # that should be always updated, right? r.data.eq(port.dat_r), # that should be always updated, right?
@ -96,7 +89,12 @@ class SRAM(Module):
ar.ready.eq(0) ar.ready.eq(0)
).Else(If(r.ready & read_fsm.ongoing("READ"), ).Else(If(r.ready & read_fsm.ongoing("READ"),
self.dout_index.eq(self.dout_index+1), self.dout_index.eq(self.dout_index+1),
port.adr.eq(port.adr + self.dout_index), # update address in the port If(ar.burst==axi.Burst.incr.value,
port.adr.eq(port.adr + self.dout_index)
).Else(If(ar.burst==axi.Burst.wrap.value,
port.adr.eq((port.adr + self.dout_index) | ar.len)
)), # update address in the port if it's incr or wrapped burst value
# no port.adr update for fixed burst type
If(self.dout_index==ar.len, r.last.eq(1)) # and update last If(self.dout_index==ar.len, r.last.eq(1)) # and update last
) )
) )
@ -104,7 +102,7 @@ class SRAM(Module):
### Write ### Write
self.comb += [ self.comb += [
w.data.eq(port.dat_w), port.dat_w.eq(w.data),
port.addr.eq(aw.addr), port.addr.eq(aw.addr),
w.strb.eq(0xff), w.strb.eq(0xff),
aw.burst.eq(axi.Burst.incr.value), aw.burst.eq(axi.Burst.incr.value),