From e38c4a14ca61888da9b28d51bcce8314b74cac8b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 2 Sep 2021 14:39:34 +0200 Subject: [PATCH] code cleanup: * moved shared init_gateware to libboard_artiq * suppressed warnings for zc706 satman --- src/libboard_artiq/Cargo.toml | 1 + src/libboard_artiq/src/lib.rs | 26 ++++++++++++++++++++++ src/runtime/src/main.rs | 28 ++--------------------- src/satman/src/main.rs | 42 ++++++++--------------------------- 4 files changed, 38 insertions(+), 59 deletions(-) diff --git a/src/libboard_artiq/Cargo.toml b/src/libboard_artiq/Cargo.toml index e6d4a96c..6bc94cab 100644 --- a/src/libboard_artiq/Cargo.toml +++ b/src/libboard_artiq/Cargo.toml @@ -17,5 +17,6 @@ core_io = { version = "0.1", features = ["collections"] } io = { path = "../libio", features = ["byteorder"] } libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"} +libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" } libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"} libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" } \ No newline at end of file diff --git a/src/libboard_artiq/src/lib.rs b/src/libboard_artiq/src/lib.rs index 0d56f02a..97258840 100644 --- a/src/libboard_artiq/src/lib.rs +++ b/src/libboard_artiq/src/lib.rs @@ -4,6 +4,7 @@ extern crate log; extern crate crc; extern crate libboard_zynq; +extern crate libregister; extern crate libconfig; extern crate libcortex_a9; extern crate log_buffer; @@ -34,6 +35,8 @@ pub mod si5324; pub mod siphaser; use core::{cmp, str}; +use libboard_zynq::slcr; +use libregister::RegisterW; pub fn identifier_read(buf: &mut [u8]) -> &str { unsafe { @@ -46,4 +49,27 @@ pub fn identifier_read(buf: &mut [u8]) -> &str { } str::from_utf8_unchecked(&buf[..len as usize]) } +} + +pub fn init_gateware() { + // Set up PS->PL clocks + slcr::RegisterBlock::unlocked(|slcr| { + // As we are touching the mux, the clock may glitch, so reset the PL. + slcr.fpga_rst_ctrl.write( + slcr::FpgaRstCtrl::zeroed() + .fpga0_out_rst(true) + .fpga1_out_rst(true) + .fpga2_out_rst(true) + .fpga3_out_rst(true) + ); + slcr.fpga0_clk_ctrl.write( + slcr::Fpga0ClkCtrl::zeroed() + .src_sel(slcr::PllSource::IoPll) + .divisor0(8) + .divisor1(1) + ); + slcr.fpga_rst_ctrl.write( + slcr::FpgaRstCtrl::zeroed() + ); + }); } \ No newline at end of file diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 52a12227..6be2867b 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -13,16 +13,15 @@ extern crate alloc; use log::{info, warn, error}; -use libboard_zynq::{timer::GlobalTimer, mpcore, gic, slcr}; +use libboard_zynq::{timer::GlobalTimer, mpcore, gic}; use libasync::{task, block_async}; use libsupport_zynq::ram; use nb; use void::Void; use embedded_hal::blocking::delay::DelayMs; use libconfig::Config; -use libregister::RegisterW; use libcortex_a9::l2c::enable_l2_cache; -use libboard_artiq::{logger, identifier_read}; +use libboard_artiq::{logger, identifier_read, init_gateware}; #[cfg(has_si5324)] use libboard_artiq::si5324; @@ -46,29 +45,6 @@ mod analyzer; mod irq; mod i2c; -fn init_gateware() { - // Set up PS->PL clocks - slcr::RegisterBlock::unlocked(|slcr| { - // As we are touching the mux, the clock may glitch, so reset the PL. - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - .fpga0_out_rst(true) - .fpga1_out_rst(true) - .fpga2_out_rst(true) - .fpga3_out_rst(true) - ); - slcr.fpga0_clk_ctrl.write( - slcr::Fpga0ClkCtrl::zeroed() - .src_sel(slcr::PllSource::IoPll) - .divisor0(8) - .divisor1(1) - ); - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - ); - }); -} - fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) { let clock_sel = if let Ok(rtioclk) = cfg.read_str("rtioclk") { diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index de66829b..010f1ef5 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -18,43 +18,18 @@ extern crate unwind; extern crate alloc; -use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio, slcr}; +use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio}; use libsupport_zynq::ram; #[cfg(has_si5324)] use libboard_artiq::si5324; -use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read}; +use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware}; use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache}; - -use embedded_hal::blocking::delay::DelayUs; - -use core::sync::atomic::{AtomicBool, Ordering}; - use libregister::{RegisterW, RegisterR}; -mod repeater; +use embedded_hal::blocking::delay::DelayUs; +use core::sync::atomic::{AtomicBool, Ordering}; -fn init_gateware() { - // Set up PS->PL clocks - slcr::RegisterBlock::unlocked(|slcr| { - // As we are touching the mux, the clock may glitch, so reset the PL. - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - .fpga0_out_rst(true) - .fpga1_out_rst(true) - .fpga2_out_rst(true) - .fpga3_out_rst(true) - ); - slcr.fpga0_clk_ctrl.write( - slcr::Fpga0ClkCtrl::zeroed() - .src_sel(slcr::PllSource::IoPll) - .divisor0(8) - .divisor1(1) - ); - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - ); - }); -} +mod repeater; fn drtiosat_reset(reset: bool) { unsafe { @@ -468,11 +443,11 @@ pub extern fn main_core0() -> i32 { let buffer_logger = unsafe { logger::BufferLogger::new(&mut LOG_BUFFER[..]) }; + //probably will have to copy init_gateware() from runtime here too buffer_logger.set_uart_log_level(log::LevelFilter::Info); buffer_logger.register(); log::set_max_level(log::LevelFilter::Info); - //probably will have to copy init_gateware() from runtime here too init_gateware(); info!("ARTIQ satellite manager starting..."); @@ -492,7 +467,6 @@ pub extern fn main_core0() -> i32 { } timer.delay_us(1500); // wait for CPLL/QPLL lock - // #[cfg(not(has_jdcg))] unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); } @@ -513,6 +487,7 @@ pub extern fn main_core0() -> i32 { loop { while !drtiosat_link_rx_up() { drtiosat_process_errors(); + #[allow(unused_mut)] for mut rep in repeaters.iter_mut() { rep.service(&routing_table, rank, &mut timer); } @@ -533,6 +508,7 @@ pub extern fn main_core0() -> i32 { while drtiosat_link_rx_up() { drtiosat_process_errors(); process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c); + #[allow(unused_mut)] for mut rep in repeaters.iter_mut() { rep.service(&routing_table, rank, &mut timer); } @@ -663,7 +639,7 @@ extern "C" { /// Called by llvm_libunwind #[no_mangle] -extern fn dl_unwind_find_exidx(pc: *const u32, len_ptr: *mut u32) -> *const u32 { +extern fn dl_unwind_find_exidx(_pc: *const u32, len_ptr: *mut u32) -> *const u32 { let length; let start: *const u32; unsafe {