From e1b2c45813e5de5587116fd5a3ad6b79dd8135e7 Mon Sep 17 00:00:00 2001 From: linuswck Date: Mon, 6 Nov 2023 16:48:37 +0800 Subject: [PATCH] kasli_soc & zc706: Fix GTX Clock Path during INIT --- src/gateware/kasli_soc.py | 18 ++++++++++++++++-- src/gateware/zc706.py | 16 ++++++++++++++-- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 4bcb8ed5..25e9c04a 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -237,12 +237,16 @@ class GenericMaster(SoCCore): gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + ext_async_rst = Signal() + self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst) self.csr_devices.append("sys_crg") self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg.cd_sys = self.sys_crg.cd_sys @@ -250,6 +254,9 @@ class GenericMaster(SoCCore): self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) fix_serdes_timing_path(platform) + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None @@ -419,12 +426,16 @@ class GenericSatellite(SoCCore): gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + ext_async_rst = Signal() + self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") @@ -433,6 +444,9 @@ class GenericSatellite(SoCCore): fix_serdes_timing_path(platform) + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + self.rtio_channels = [] has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) if has_grabber: diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index f9556e6b..92c92084 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -226,6 +226,7 @@ class _MasterBase(SoCCore): self.csr_devices.append("gt_drtio") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + ext_async_rst = Signal() txout_buf = Signal() gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) @@ -234,12 +235,17 @@ class _MasterBase(SoCCore): self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done, + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst, freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + drtio_csr_group = [] drtioaux_csr_group = [] drtioaux_memory_group = [] @@ -361,6 +367,7 @@ class _SatelliteBase(SoCCore): clk_freq=clk_freq) self.csr_devices.append("gt_drtio") + ext_async_rst = Signal() txout_buf = Signal() txout_buf.attr.add("keep") gtx0 = self.gt_drtio.gtxs[0] @@ -373,12 +380,17 @@ class _SatelliteBase(SoCCore): self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done, + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst, freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = []