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KasliSoC satellite: fix serdes timing

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mwojcik 2023-02-20 13:06:31 +08:00 committed by Gitea
parent d72a2e7d07
commit dce37a52aa
1 changed files with 2 additions and 0 deletions
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src/gateware/kasli_soc.py
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@ -342,6 +342,8 @@ class GenericSatellite(SoCCore):
self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg = self.ps7 # HACK for eem_7series to find the clock
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
fix_serdes_timing_path(platform)
self.rtio_channels = [] self.rtio_channels = []
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
if has_grabber: if has_grabber: