From d1705113aaab6eb077aa7a121a67ba0bc8f1bc9b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 6 Aug 2021 10:05:45 +0200 Subject: [PATCH] kasli: gtx transcvr expects separate tx/rx pads --- src/gateware/kasli_soc.py | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 57af793f..51276308 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -210,10 +210,19 @@ class GenericMaster(SoCCore): # kasli_soc has no SATA, but it has 4x SFP # not sure yet why sfp0 is omitted in MasterMode drtio_data_pads = [platform.request("sfp", i) for i in range(4)] + drtio_tx_pads = [] + drtio_rx_pads = [] + for sfp in drtio_data_pads: + drtio_tx_pads += [sfp.txp, sfp.txn] + drtio_rx_pads += [sfp.rxp, sfp.rxn] + # this does not work for now ^ GTX expects p/n subsignals in tx/rx signals, + # rather than txp/txn ... subsignals + # probably need to modify kasli_soc platform in migen self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? - data_pads=drtio_data_pads, + tx_pads=drtio_tx_pads, + rx_pads=drtio_rx_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") @@ -344,10 +353,16 @@ class GenericSatellite(SoCCore): platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") drtio_data_pads = [platform.request("sfp", i) for i in range(4)] - + drtio_tx_pads = [] + drtio_rx_pads = [] + for sfp in drtio_data_pads: + drtio_tx_pads += [sfp.txp, sfp.txn] + drtio_rx_pads += [sfp.rxp, sfp.rxn] + self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? - data_pads=drtio_data_pads, + tx_pads=drtio_tx_pads, + rx_pads=drtio_rx_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver")