From cafbe97e47520572d00cc10fdfd438a9029c6c61 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Fri, 30 Jul 2021 15:14:40 +0200
Subject: [PATCH] zc706: added targets to default.nix, fixed wrong base cls

---
 default.nix           |  4 ++++
 src/gateware/zc706.py | 12 ++++++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/default.nix b/default.nix
index 2b8394a0..022892ad 100644
--- a/default.nix
+++ b/default.nix
@@ -134,9 +134,13 @@ in
     (build { target = "zc706"; variant = "simple"; }) //
     (build { target = "zc706"; variant = "nist_clock"; }) //
     (build { target = "zc706"; variant = "nist_qc2"; }) //
+    (build { target = "zc706"; variant = "master"; }) //
+    (build { target = "zc706"; variant = "satellite"; }) //
     (build { target = "zc706"; variant = "acpki_simple"; }) //
     (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
     (build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
+    (build { target = "zc706"; variant = "acpki_master"; }) //
+    (build { target = "zc706"; variant = "acpki_satellite"; }) //
     (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
     { inherit zynq-rs; }
   )
diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index bafc8f61..5d129841 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -307,7 +307,7 @@ class Master(ZC706):
         "rtio_dma":     0x30000000,
         "drtioaux":     0x50000000,
     }
-    mem_map.update(BaseSoC.mem_map)
+    mem_map.update(SoCCore.mem_map)
 
     def __init__(self, **kwargs):
         ZC706.__init__(self, **kwargs)
@@ -316,10 +316,10 @@ class Master(ZC706):
 
         self.comb += platform.request("sfp_tx_disable_n").eq(1)
         tx_pads = [
-            platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
+            platform.request("sfp_tx")
         ]
         rx_pads = [
-            platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
+            platform.request("sfp_rx")
         ]
 
         # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
@@ -369,7 +369,6 @@ class Master(ZC706):
         self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        # i2c not supported? todo - figure out if it should be
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
 
@@ -407,6 +406,11 @@ class Master(ZC706):
         self.add_rtio(rtio_channels)
 
 class Satellite(ZC706):
+    mem_map = {
+        "drtioaux":     0x50000000,
+    }
+    mem_map.update(SoCCore.mem_map)
+
     def __init__(self, **kwargs):
         ZC706.__init__(self, **kwargs)