diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py
index cf06968f..86b696ab 100644
--- a/src/gateware/aux_controller.py
+++ b/src/gateware/aux_controller.py
@@ -36,8 +36,6 @@ class SRAM(Module):
 
         # probably will get removed
         self.addr_base = CSRStorage(32)
-        self.trig_count = CSRStatus(32)
-        self.write_count = CSRStatus(32)
 
         self.trigger_stb = Signal()
 
@@ -47,11 +45,8 @@ class SRAM(Module):
         # data
         #
         # Cycle:
-        # trigger_stb pulsed at start
         # Then out_burst_len words are strobed out of dout
         # Then, when din_ready is high, in_burst_len words are strobed in to din
-        self.dout_stb = Signal() # there's no strobe signal for SRAM
-        self.din_stb = Signal()
         self.dout_index = Signal(bus_addr_width)  # is this legal?
         self.din_index = Signal(bus_addr_width)
         self.din_ready = Signal()
@@ -65,8 +60,8 @@ class SRAM(Module):
 
         ### Read
         self.comb += [
-            ar.addr.eq(port.adr),  # shouldn't it be the other way around?
-            port.dat_r.eq(r.data),
+            port.adr.eq(ar.addr),
+            r.data.eq(port.dat_r),
             r.ready.eq(1),
             ar.burst.eq(axi.Burst.incr.value),
             ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
@@ -77,45 +72,41 @@ class SRAM(Module):
         # read control
         self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
         read_fsm.act("IDLE",
-            If(self.trigger_stb,
-                ar.valid.eq(1),
-                If(ar.ready,
-                    NextState("READ")
-                ).Else(
-                    NextState("READ_START")
-                )
+            If(ar.valid,
+                ar.ready.eq(1),
+                NextState("READ_START"),
             )
         )
         read_fsm.act("READ_START",
-            ar.valid.eq(1),
-            If(ar.ready,
-                NextState("READ"),
-            )
+            If(r.valid,
+                r.ready.eq(1),
+                r.data.eq(port.dat_r), # that should be always updated, right?
+                NextState("READ"))
         )
         read_fsm.act("READ",
-            ar.valid.eq(0),
-            If(r.last & r.valid,
+            If(r.last & r.valid, # that's a smart way of skipping "LAST" state
+                r.data.eq(port.dat_r),
                 NextState("IDLE")
             )
         )
 
         self.sync += [
             If(read_fsm.ongoing("IDLE"),
-                self.dout_index.eq(0) 
+                self.dout_index.eq(0),
+                r.ready.eq(0),  # shall it be reset too on IDLE?
+                ar.ready.eq(0)
             ).Else(If(r.valid & read_fsm.ongoing("READ"),
                     self.dout_index.eq(self.dout_index+1),
-                    port.adr.eq(port.adr + self.dout_index) # update address in the port
+                    port.adr.eq(port.adr + self.dout_index), # update address in the port
+                    If(self.dout_index==ar.len, r.last.eq(1)) # and update last
                 )
             )
         ]
 
-        # possibly unnecessary too
-        self.comb += self.dout_stb.eq(r.valid & r.ready)
-
         ### Write
         self.comb += [
             w.data.eq(port.dat_w),
-            aw.addr.eq(port.addr), # shouldn't it be the other way around?
+            port.addr.eq(aw.addr),
             w.strb.eq(0xff),
             aw.burst.eq(axi.Burst.incr.value),
             aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
@@ -172,9 +163,6 @@ class SRAM(Module):
             If(self.din_index==aw.len, w.last.eq(1))
         ]
 
-        # check if necessary
-        self.comb += self.din_stb.eq(w.valid & w.ready)
-
 
         # # generate write enable signal
         # if not read_only: