From b6dd5bea683a3ad7f90123c90a445dd6fcfd9833 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 13 Aug 2021 14:58:18 +0200 Subject: [PATCH] sram: fixed wrong assumptions on some signals --- src/gateware/aux_controller.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py index 86b696ab..76d6ce6c 100644 --- a/src/gateware/aux_controller.py +++ b/src/gateware/aux_controller.py @@ -37,8 +37,6 @@ class SRAM(Module): # probably will get removed self.addr_base = CSRStorage(32) - self.trigger_stb = Signal() - # Dout : Data received from CPU, output by SRAM <- port.dat_r # Din : Data driven into SRAM, written into CPU <- port.dat_w # When stb assert, index shows word being read/written, dout/din holds <- will be removed @@ -78,14 +76,15 @@ class SRAM(Module): ) ) read_fsm.act("READ_START", - If(r.valid, - r.ready.eq(1), + r.data.eq(port.dat_r), + r.valid.eq(1), + If(r.ready, r.data.eq(port.dat_r), # that should be always updated, right? NextState("READ")) ) read_fsm.act("READ", - If(r.last & r.valid, # that's a smart way of skipping "LAST" state - r.data.eq(port.dat_r), + r.data.eq(port.dat_r), + If(r.last & r.ready, # that's a smart way of skipping "LAST" state NextState("IDLE") ) ) @@ -95,7 +94,7 @@ class SRAM(Module): self.dout_index.eq(0), r.ready.eq(0), # shall it be reset too on IDLE? ar.ready.eq(0) - ).Else(If(r.valid & read_fsm.ongoing("READ"), + ).Else(If(r.ready & read_fsm.ongoing("READ"), self.dout_index.eq(self.dout_index+1), port.adr.eq(port.adr + self.dout_index), # update address in the port If(self.dout_index==ar.len, r.last.eq(1)) # and update last