From b585eaaa37ee404e87d263efc4f8021ad348238a Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 24 Aug 2021 13:51:38 +0200 Subject: [PATCH] zc706: added memory iface generator --- src/gateware/zc706.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index f333e82f..fb491b1a 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -530,6 +530,11 @@ def write_csr_file(soc, filename): f.write(cpu_interface.get_csr_rust( soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) +def write_mem_file(soc, filename): + with open(filename, "w") as f: + f.write(cpu_interface.get_mem_rust( + soc.get_memory_regions(), soc.get_memory_groups(), None)) + def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: @@ -545,6 +550,8 @@ def main(): description="ARTIQ port to the ZC706 Zynq development kit") parser.add_argument("-r", default=None, help="build Rust interface into the specified file") + parser.add_argument("-m", default=None, + help="build Rust memory interface into the specified file") parser.add_argument("-c", default=None, help="build Rust compiler configuration into the specified file") parser.add_argument("-g", default=None, @@ -567,8 +574,12 @@ def main(): soc = cls(acpki=acpki) soc.finalize() + print(soc.get_memory_regions()) + if args.r is not None: write_csr_file(soc, args.r) + if args.m is not None: + write_mem_file(soc, args.m) if args.c is not None: write_rustc_cfg_file(soc, args.c) if args.g is not None: