diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 5d129841..0311a40c 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -126,49 +126,6 @@ class ZC706(SoCCore):
                                                           self.ps7.s_axi_hp1)
         self.csr_devices.append("rtio_analyzer")
 
-    def add_drtio(self):
-        platform = self.platform
-
-
-
-        drtio_csr_group = []
-        drtioaux_csr_group = []
-        drtioaux_memory_group = []
-        drtio_cri = []
-
-        for i in range(len(self.drtio_transceiver.channels)):
-            core_name = "drtio" + str(i)
-            coreaux_name = "drtioaux" + str(i)
-            memory_name = "drtioaux" + str(i) + "_mem"
-            drtio_csr_group.append(core_name)
-            drtioaux_csr_group.append(coreaux_name)
-            drtioaux_memory_group.append(memory_name)
-
-            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
-
-            core = cdr(DRTIOMaster(
-                self.rtio_tsc, self.drtio_transceiver.channels[i]))
-            setattr(self.submodules, core_name, core)
-            drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
-
-            coreaux = cdr(DRTIOAuxController(core.link_layer))
-            setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
-
-            memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.add_wb_slave(memory_address, 0x800,
-                              coreaux.bus)
-            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
-        
-        self.rustc_cfg["HAS_DRTIO"] = None
-        self.rustc_cfg["HAS_DRTIO_ROUTING"] = None
-        self.add_csr_group("drtio", drtio_csr_group)
-        self.add_csr_group("drtioaux", drtioaux_csr_group)
-        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-
-
-
 
 class Simple(ZC706):
     def __init__(self, **kwargs):