From b13da96835c83c44ebc3fbf022b7e9bae80a2af7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 7 Jul 2020 17:22:07 +0800 Subject: [PATCH] increase CSR bus width to 32 bits Before: Minimum interval for sustained TTL output switching ... 1.554e-06 After: Minimum interval for sustained TTL output switching ... 5.17e-07 --- src/zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/zc706.py b/src/zc706.py index 15f2bf65..20f70e85 100755 --- a/src/zc706.py +++ b/src/zc706.py @@ -18,7 +18,7 @@ class ZC706(SoCCore): platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) - SoCCore.__init__(self, platform=platform, ident=self.__class__.__name__) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__) platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")