diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 01b28e31..68c9ff80 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
+from misoc.cores import gpio
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
@@ -329,12 +330,6 @@ class Master(ZC706):
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
 
-        user_sma_clock = platform.request("user_sma_clock")
-        self.comb += [
-            user_sma_clock.p.eq(ClockSignal("rtio_rx0")),
-            user_sma_clock.n.eq(ClockSignal("rtio"))
-        ]
-
         rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
         # (First channel acts as master for phase alignment for all channels' TX)
@@ -342,14 +337,14 @@ class Master(ZC706):
         platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
         platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
         platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
+            self.ps7.cd_sys.clk,
             gtx0.txoutclk, gtx0.rxoutclk)
         # Constrain RX timing for the each transceiver channel
         # (Each channel performs single-lane phase alignment for RX)
         for gtx in self.drtio_transceiver.gtxs[1:]:
             platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
             platform.add_false_path_constraints(
-                self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
+                self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
 
         rtio_channels = []
         for i in range(4):
@@ -442,22 +437,12 @@ class Satellite(ZC706):
             ultrascale=False,
             rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
         platform.add_false_path_constraints(
-            self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
+            self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
         self.csr_devices.append("siphaser")
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        i2c = self.platform.request("i2c")
-        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
-        self.csr_devices.append("i2c")
-        self.config["I2C_BUS_COUNT"] = 1
         self.config["HAS_SI5324"] = None
 
-        user_sma_clock = platform.request("user_sma_clock")
-        self.comb += [
-            user_sma_clock.p.eq(ClockSignal("rtio_rx0")),
-            user_sma_clock.n.eq(ClockSignal("rtio"))
-        ]
-
         rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
         # (First channel acts as master for phase alignment for all channels' TX)
@@ -465,14 +450,14 @@ class Satellite(ZC706):
         platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
         platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
         platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
+            self.ps7.cd_sys.clk,
             gtx0.txoutclk, gtx0.rxoutclk)
         # Constrain RX timing for the each transceiver channel
         # (Each channel performs single-lane phase alignment for RX)
         for gtx in self.drtio_transceiver.gtxs[1:]:
             platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
             platform.add_false_path_constraints(
-                self.crg.cd_sys.clk, gtx.rxoutclk)
+                self.ps7.cd_sys.clk, gtx.rxoutclk)
 
         rtio_channels = []
         for i in range(4):
@@ -501,6 +486,7 @@ class Satellite(ZC706):
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.drtiosat.cri],
             [self.local_io.cri] + self.drtio_cri,