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libboard_artiq: added mem.rs, yet to fix drtioaux

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This commit is contained in:
mwojcik 2021-08-24 14:11:30 +02:00
parent 37eb4669fb
commit a8a2da575b
2 changed files with 15 additions and 13 deletions
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19
src/libboard_artiq/src/drtioaux.rs
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@ -1,35 +1,28 @@
use core::slice; use core::slice;
use crc; use crc;
use io::{ProtoRead, ProtoWrite, Cursor, Error as IoError}; use io::{ProtoRead, ProtoWrite, Cursor, Error as IoError};
//use board_misoc::{mem::DRTIOAUX_MEM}; // <- port use mem::mem::DRTIOAUX_MEM;
//^ uses generated files (like csr, but mem) - todo check after initial generation
use pl::csr::DRTIOAUX; use pl::csr::DRTIOAUX;
use drtioaux_proto::Error as ProtocolError; use crate::drtioaux_proto::Error as ProtocolError;
use libboard_zynq::{timer::GlobalTimer, time::Milliseconds}; use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
pub use drtioaux_proto::Packet; pub use crate::drtioaux_proto::Packet;
// this is parametric over T because there's no impl Fail for !. // this is parametric over T because there's no impl Fail for !.
#[derive(Fail, Debug)] #[derive(Debug)]
pub enum Error<T> { pub enum Error<T> {
#[fail(display = "gateware reported error")]
GatewareError, GatewareError,
#[fail(display = "packet CRC failed")]
CorruptedPacket, CorruptedPacket,
#[fail(display = "link is down")]
LinkDown, LinkDown,
#[fail(display = "timed out waiting for data")]
TimedOut, TimedOut,
#[fail(display = "unexpected reply")]
UnexpectedReply, UnexpectedReply,
#[fail(display = "routing error")]
RoutingError, RoutingError,
#[fail(display = "protocol error: {}", _0)] Protocol(ProtocolError<T>)
Protocol(#[cause] ProtocolError<T>)
} }
impl<T> From<ProtocolError<T>> for Error<T> { impl<T> From<ProtocolError<T>> for Error<T> {

9
src/libboard_artiq/src/lib.rs
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@ -2,10 +2,14 @@
#![feature(never_type)] #![feature(never_type)]
extern crate log; extern crate log;
extern crate crc;
extern crate failure;
extern crate failure_derive;
extern crate libboard_zynq; extern crate libboard_zynq;
extern crate libconfig; extern crate libconfig;
extern crate libcortex_a9; extern crate libcortex_a9;
extern crate log_buffer; extern crate log_buffer;
extern crate io;
// has csr; taken from runtime main // has csr; taken from runtime main
#[path = "../../../build/pl.rs"] #[path = "../../../build/pl.rs"]
@ -13,6 +17,11 @@ pub mod pl;
#[cfg(has_drtio)] #[cfg(has_drtio)]
pub mod drtioaux; pub mod drtioaux;
// for now, memory map is only needed for DRTIO firmware
#[cfg(has_drtio)]
#[path = "../../../build/mem.rs"]
pub mod mem;
pub mod drtio_routing; pub mod drtio_routing;
pub mod logger; pub mod logger;