From 9c092162819d049c9e0b5537b594da2c2bc38e52 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 13 Sep 2021 15:06:34 +0200 Subject: [PATCH] updated gateware for not yet published migen-axi changes --- src/gateware/aux_controller.py | 9 +++++++++ src/gateware/kasli_soc.py | 20 ++++++-------------- src/gateware/zc706.py | 17 ++++++----------- 3 files changed, 21 insertions(+), 25 deletions(-) diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py index 66626864..efb41adb 100644 --- a/src/gateware/aux_controller.py +++ b/src/gateware/aux_controller.py @@ -44,3 +44,12 @@ class DRTIOAuxControllerBare(Module): def get_csrs(self): return self.transmitter.get_csrs() + self.receiver.get_csrs() + + def get_tx_port(self): + return self.transmitter.mem.get_port(write_capable=True) + + def get_rx_port(self): + return self.receiver.mem.get_port(write_capable=False) + + def get_mem_size(self): + return max_packet diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 0fabcd95..c6811418 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -208,13 +208,6 @@ class GenericStandalone(SoCCore): class GenericMaster(SoCCore): - mem_map = { - # "cri_con": 0x10000000, - # "rtio": 0x20000000, - # "rtio_dma": 0x30000000, - "drtioaux": 0x40000000 - } - mem_map.update(SoCCore.mem_map) def __init__(self, description, acpki=False): sys_clk_freq = 125e6 @@ -344,10 +337,6 @@ class GenericMaster(SoCCore): class GenericSatellite(SoCCore): - mem_map = { - "drtioaux": 0x40000000 - } - mem_map.update(SoCCore.mem_map) def __init__(self, description, acpki=False): sys_clk_freq = 125e6 @@ -433,12 +422,15 @@ class GenericSatellite(SoCCore): setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) - memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False) + mem_size = coreaux.get_mem_size() + tx_port = coreaux.get_tx_port() + rx_port = coreaux.get_rx_port() + memory_address = self.axi2csr.register_port(tx_port, mem_size) # rcv in upper half of the memory, thus added second - self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False) + self.axi2csr.register_port(rx_port, mem_size) # and registered in PS interface # manually, because software refers to rx/tx by halves of entire memory block, not names - self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2) + self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) self.config["has_drtio"] = None self.config["has_drtio_routing"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 26a4e769..1e599aec 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -170,10 +170,6 @@ class ZC706(SoCCore): self.csr_devices.append("rtio_analyzer") class _MasterBase(SoCCore): - mem_map = { - "drtioaux": 0x40000000, - } - mem_map.update(SoCCore.mem_map) def __init__(self, acpki=False): self.acpki = acpki @@ -268,10 +264,6 @@ class _MasterBase(SoCCore): class _SatelliteBase(SoCCore): - mem_map = { - "drtioaux": 0x40000000, - } - mem_map.update(SoCCore.mem_map) def __init__(self, acpki=False): self.acpki = acpki @@ -334,12 +326,15 @@ class _SatelliteBase(SoCCore): setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) - memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False) + mem_size = coreaux.get_mem_size() + tx_port = coreaux.get_tx_port() + rx_port = coreaux.get_rx_port() + memory_address = self.axi2csr.register_port(tx_port, mem_size) # rcv in upper half of the memory, thus added second - self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False) + self.axi2csr.register_port(rx_port, mem_size) # and registered in PS interface # manually, because software refers to rx/tx by halves of entire memory block, not names - self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2) + self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) self.rustc_cfg["has_drtio"] = None # it does not have drtio routing support! self.add_csr_group("drtioaux", drtioaux_csr_group)