From 97dfa07bdb78cfcef23ae555167d82292042daf7 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 6 Aug 2021 10:05:04 +0200 Subject: [PATCH] determined probable sys_clk_freq for GTX transcvr --- src/gateware/kasli_soc.py | 13 ++++++++++--- src/gateware/zc706.py | 9 +++++++-- src/satman/main.rs | 3 ++- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 0b0d514d..57af793f 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -187,6 +187,9 @@ class GenericMaster(SoCCore): mem_map.update(SoCCore.mem_map) def __init__(self, description, acpki=False): + sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL? + # not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly + # necessary for GTX transceiver rtio_clk_freq = 125e6 # should this be pulled from description? rtio freq isnt set self.acpki = acpki @@ -211,7 +214,7 @@ class GenericMaster(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? data_pads=drtio_data_pads, - sys_clk_freq=self.clk_freq) + sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") self.crg = self.ps7 # HACK for eem_7series to find the clock @@ -319,7 +322,11 @@ class GenericSatellite(SoCCore): mem_map.update(SoCCore.mem_map) def __init__(self, description, acpki=False): - rtio_clk_freq = 125e6 # same thing as with master + sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL? + # not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly + # necessary for GTX transceiver + rtio_clk_freq = 125e6 # same thing as with master - pulled from desc? + # will probably be replaced with rtio_config key as per #1735 self.acpki = acpki self.rustc_cfg = dict() @@ -341,7 +348,7 @@ class GenericSatellite(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? data_pads=drtio_data_pads, - sys_clk_freq=self.clk_freq) + sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") self.crg = self.ps7 # HACK for eem_7series to find the clock diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 0311a40c..b6be69a5 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -269,6 +269,9 @@ class Master(ZC706): def __init__(self, **kwargs): ZC706.__init__(self, **kwargs) + sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL + # again not sure if correct value + platform = self.platform self.comb += platform.request("sfp_tx_disable_n").eq(1) @@ -284,7 +287,7 @@ class Master(ZC706): clock_pads=platform.request("si5324_clkout"), tx_pads=tx_pads, rx_pads=rx_pads, - sys_clk_freq=self.clk_freq) + sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) @@ -370,6 +373,8 @@ class Satellite(ZC706): def __init__(self, **kwargs): ZC706.__init__(self, **kwargs) + sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL + # again not sure if correct value platform = self.platform @@ -386,7 +391,7 @@ class Satellite(ZC706): clock_pads=platform.request("si5324_clkout"), tx_pads=tx_pads, rx_pads=rx_pads, - sys_clk_freq=self.clk_freq) + sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) diff --git a/src/satman/main.rs b/src/satman/main.rs index 2f2f0c8c..b05715f3 100644 --- a/src/satman/main.rs +++ b/src/satman/main.rs @@ -16,7 +16,7 @@ extern crate libregister; extern crate alloc; -use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic}; +use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio}; use libsupport_zynq::ram; #[cfg(has_si5324)] use libboard_artiq::si5324; @@ -580,6 +580,7 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, { notify_spin_lock(); main_core1(); } + stdio::drop_uart(); } loop {} });