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aux_controller: connect r/w/b lanes to axi bus

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mwojcik 2021-09-29 11:50:52 +02:00
parent b9f0bb3899
commit 8ab2b3f299
1 changed files with 31 additions and 0 deletions
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31
src/gateware/aux_controller.py
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@ -28,6 +28,37 @@ class DRTIOAuxControllerAxi(Module):
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)],
register=True)
# unlike wb, axi address decoder only connects ar/aw lanes,
# the rest must also be connected!
# connect bus.b with tx.b
self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
self.bus.b.id.eq(tx_sdram_if.bus.b.id),
self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
# connect bus.w with tx.w
# no worries about w.valid and slave sel here, only tx will be written to
self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
tx_sdram_if.bus.w.data.eq(self.bus.w.data),
tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
tx_sdram_if.bus.w.last.eq(self.bus.w.last),
tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
# connect bus.r with rx.r and tx.r
self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id),
self.bus.r.data.eq(rx_sdram_if.bus.r.data),
self.bus.r.resp.eq(rx_sdram_if.bus.r.resp),
self.bus.r.last.eq(rx_sdram_if.bus.r.last),
self.bus.r.valid.eq(rx_sdram_if.bus.r.valid),
rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
self.bus.r.id.eq(tx_sdram_if.bus.r.id),
self.bus.r.data.eq(tx_sdram_if.bus.r.data),
self.bus.r.resp.eq(tx_sdram_if.bus.r.resp),
self.bus.r.last.eq(tx_sdram_if.bus.r.last),
self.bus.r.valid.eq(tx_sdram_if.bus.r.valid),
tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
def get_csrs(self):