From 7ff59f57a9ce512f30094ab8d52ee95d76116769 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Aug 2021 15:11:21 +0200 Subject: [PATCH] gateware: updated gtx interface --- src/gateware/kasli_soc.py | 23 ++++------------------- src/gateware/zc706.py | 20 ++++++-------------- 2 files changed, 10 insertions(+), 33 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 7140782c..29907c15 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -207,20 +207,11 @@ class GenericMaster(SoCCore): # kasli_soc has no SATA, but it has 4x SFP # not sure yet why sfp0 is omitted in MasterMode - drtio_data_pads = [platform.request("sfp", i) for i in range(4)] - drtio_tx_pads = [] - drtio_rx_pads = [] - for sfp in drtio_data_pads: - drtio_tx_pads += [sfp.txp, sfp.txn] - drtio_rx_pads += [sfp.rxp, sfp.rxn] - # this does not work for now ^ GTX expects p/n subsignals in tx/rx signals, - # rather than txp/txn ... subsignals - # probably need to modify kasli_soc platform in migen + data_pads = [platform.request("sfp", i) for i in range(4)] self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? - tx_pads=drtio_tx_pads, - rx_pads=drtio_rx_pads, + pads=data_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") @@ -346,17 +337,11 @@ class GenericSatellite(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - drtio_data_pads = [platform.request("sfp", i) for i in range(4)] - drtio_tx_pads = [] - drtio_rx_pads = [] - for sfp in drtio_data_pads: - drtio_tx_pads += [sfp.txp, sfp.txn] - drtio_rx_pads += [sfp.rxp, sfp.rxn] + data_pads = [platform.request("sfp", i) for i in range(4)] self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? - tx_pads=drtio_tx_pads, - rx_pads=drtio_rx_pads, + pads=data_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index d4b25cfc..021fa4d2 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -275,18 +275,14 @@ class Master(ZC706): platform = self.platform self.comb += platform.request("sfp_tx_disable_n").eq(1) - tx_pads = [ - platform.request("sfp_tx") - ] - rx_pads = [ - platform.request("sfp_rx") + data_pads = [ + platform.request("sfp") ] # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), - tx_pads=tx_pads, - rx_pads=rx_pads, + pads=data_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") @@ -372,18 +368,14 @@ class Satellite(ZC706): platform = self.platform self.comb += platform.request("sfp_tx_disable_n").eq(1) - tx_pads = [ - platform.request("sfp_tx") - ] - rx_pads = [ - platform.request("sfp_rx") + data_pads = [ + platform.request("sfp") ] # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), - tx_pads=tx_pads, - rx_pads=rx_pads, + pads=data_pads, sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver")