forked from M-Labs/artiq-zynq
zynq_clocking: expose mmcm_locked for SYSCRG
- mmcm_locked -> self.mmcm_locked
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parent
d3f4602361
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79fc5a7789
@ -88,7 +88,7 @@ class SYSCRG(Module, AutoCSR):
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else:
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
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mmcm_locked = Signal()
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self.mmcm_locked = Signal()
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mmcm_sys = Signal()
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mmcm_sys4x = Signal()
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mmcm_sys5x = Signal()
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@ -96,7 +96,7 @@ class SYSCRG(Module, AutoCSR):
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mmcm_fb_clk = Signal()
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self.specials += [
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Instance("MMCME2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked,
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.mmcm_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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@ -125,8 +125,8 @@ class SYSCRG(Module, AutoCSR):
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~mmcm_locked),
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
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]
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reset_counter = Signal(4, reset=15)
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