Merge branch 'master' into drtio_port

src/gateware/kasli_soc.py

@@ -33,6 +33,15 @@ class RTIOCRG(Module, AutoCSR):
         self.clock_domains.cd_rtio = ClockDomain()
         self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
 
+        clk_synth = platform.request("cdr_clk_clean_fabric")
+        clk_synth_se = Signal()
+        platform.add_period_constraint(clk_synth.p, 8.0)
+        self.specials += [
+            Instance("IBUFGDS",
+                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
+        ]
+
         pll_locked = Signal()
         rtio_clk = Signal()
         rtiox4_clk = Signal()
@@ -43,7 +52,7 @@ class RTIOCRG(Module, AutoCSR):
                      p_BANDWIDTH="HIGH",
                      p_REF_JITTER1=0.001,
                      p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
-                     i_CLKIN2=ClockSignal(),
+                     i_CLKIN2=clk_synth_se,
                      # Warning: CLKINSEL=0 means CLKIN2 is selected
                      i_CLKINSEL=0,
 

src/libboard_artiq/src/si5324.rs

@@ -170,7 +170,6 @@ fn monitor_lock(i2c: &mut I2c) -> Result<()> {
 }
 
 fn init(i2c: &mut I2c) -> Result<()> {
-    info!("init test");
     #[cfg(feature = "target_kasli_soc")]
     {
         i2c.pca9548_select(0x70, 0)?;

src/runtime/src/main.rs

@@ -185,9 +185,9 @@ pub fn main_core0() {
     info!("detected gateware: {}", identifier_read(&mut [0; 64]));
 
     i2c::init();
-    /*#[cfg(feature = "target_kasli_soc")]
+    #[cfg(feature = "target_kasli_soc")]
     si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
-        &SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");*/
+        &SI5324_SETTINGS, si5324::Input::Ckin2).expect("cannot initialize Si5324");
 
     let cfg = match Config::new() {
         Ok(cfg) => cfg,