From 3e1d14ff388dc64f1bd0df1936cead9422ddac20 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Mon, 16 Aug 2021 15:33:50 +0200
Subject: [PATCH] replaced increment logic with ready Incr module

---
 src/gateware/aux_controller.py | 43 ++++++++++++----------------------
 1 file changed, 15 insertions(+), 28 deletions(-)

diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py
index c6427dc6..b0db3899 100644
--- a/src/gateware/aux_controller.py
+++ b/src/gateware/aux_controller.py
@@ -36,10 +36,6 @@ class SRAM(Module):
 
         # Dout : Data received from CPU, output by SRAM <- port.dat_r
         # Din : Data driven into SRAM, written into CPU <- port.dat_w
-        #
-        # Cycle:
-        # Then out_burst_len words are strobed out of dout
-        # Then, when din_ready is high, in_burst_len words are strobed in to din
         self.dout_index = Signal(bus_addr_width)  # is this legal?
         self.din_index = Signal(bus_addr_width)
         self.din_ready = Signal()
@@ -48,21 +44,17 @@ class SRAM(Module):
 
         ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
 
+        self.r_addr_incr = axi.Incr(ar)
+
         ### Read
-        self.comb += [
-            port.adr.eq(ar.addr), # still not sure if legal hm
-            r.data.eq(port.dat_r),
-            # r.ready.eq(1),
-            # ar.burst.eq(axi.Burst.incr.value),
-            # ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
-            # ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
-            # ar.cache.eq(0xf),
-        ]
+
+        self.comb += r.data.eq(port.dat_r) 
 
         # read control
         self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
         read_fsm.act("IDLE",
             If(ar.valid,
+                port.adr.eq(self.r_addr_incr.addr),
                 ar.ready.eq(1),
                 NextState("READ_START"),
             )
@@ -85,16 +77,11 @@ class SRAM(Module):
         self.sync += [
             If(read_fsm.ongoing("IDLE"),
                 self.dout_index.eq(0),
-                r.ready.eq(0),  # shall it be reset too on IDLE?
-                ar.ready.eq(0)
+                r.valid.eq(0),  # shall it be reset too on IDLE?
+                ar.ready.eq(0),
             ).Else(If(r.ready & read_fsm.ongoing("READ"),
                     self.dout_index.eq(self.dout_index+1),
-                    If(ar.burst==axi.Burst.incr.value, 
-                        port.adr.eq(port.adr + self.dout_index)
-                    ).Else(If(ar.burst==axi.Burst.wrap.value,
-                        port.adr.eq(port.adr + (self.dout_index | ar.len))
-                    )), # update address in the port if it's incr or wrapped burst value
-                    # no port.adr update for fixed burst type
+                    port.adr.eq(self.r_addr_incr.addr),
                     If(self.dout_index==ar.len, r.last.eq(1)) # and update last
                 )
             )
@@ -104,12 +91,12 @@ class SRAM(Module):
         self.comb += [
             port.dat_w.eq(w.data),
             port.addr.eq(aw.addr),
-            w.strb.eq(0xff),
-            aw.burst.eq(axi.Burst.incr.value),
-            aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
-            aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
-            aw.cache.eq(0xf),
-            b.ready.eq(1),
+            # w.strb.eq(0xff),
+            # aw.burst.eq(axi.Burst.incr.value),
+            # aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
+            # aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
+            # aw.cache.eq(0xf),
+            # b.ready.eq(1),
         ]
 
         self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
@@ -150,7 +137,7 @@ class SRAM(Module):
 
         self.sync += [
             If(write_fsm.ongoing("IDLE"),
-                self.din_index.eq(0) # replace with address?
+                self.din_index.eq(0) 
             ), # but need to synchronise the address too
             If(w.ready & w.valid, self.din_index.eq(self.din_index+1), port.adr.eq(port.addr+self.din_index))
         ]