From 3ba7fe1e6b9c75895b4c984c5ffd4244ed806d77 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 30 Jul 2021 12:52:58 +0200 Subject: [PATCH] kasli_soc uses gtx transceiver instead of gtp --- src/gateware/kasli_soc.py | 46 +++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 51a9fb0d..dee2bdc1 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -16,7 +16,7 @@ from artiq.coredevice import jsondesc from artiq.gateware import rtio, eem_7series from artiq.gateware.rtio.phy import ttl_simple -from artiq.gateware.drtio.transceiver import gtp_7series +from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio import * @@ -167,6 +167,9 @@ class GenericStandalone(SoCCore): class GenericMaster(SoCCore): mem_map = { + "cri_con": 0x10000000, + "rtio": 0x20000000, + "rtio_dma": 0x30000000, "drtioaux": 0x50000000 } mem_map.update(SoCCore.mem_map) @@ -193,11 +196,10 @@ class GenericMaster(SoCCore): # not sure yet why sfp0 is omitted in MasterMode drtio_data_pads = [platform.request("sfp", i) for i in range(4)] - self.submodules.drtio_transceiver = gtp_7series.GTP( - qpll_channel=self.drtio_qpll_channel, # todo figure out qpll + self.submodules.drtio_transceiver = gtx_7series.GTX( + clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? data_pads=drtio_data_pads, - sys_clk_freq=self.clk_freq, - rtio_clk_freq=rtio_clk_freq) + sys_clk_freq=self.clk_freq) self.csr_devices.append("drtio_transceiver") # todo figure out cdr lk clean # self.sync += self.disable_cdr_clk_ibuf.eq( @@ -333,11 +335,10 @@ class GenericSatellite(SoCCore): drtio_data_pads = [platform.request("sfp", i) for i in range(4)] - self.submodules.drtio_transceiver = gtp_7series.GTP( - qpll_channel=qpll.channels[0], # todo - figure out qpll + self.submodules.drtio_transceiver = gtx_7series.GTX( + clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? data_pads=drtio_data_pads, - sys_clk_freq=self.clk_freq, - rtio_clk_freq=rtio_clk_freq) + sys_clk_freq=self.clk_freq) self.csr_devices.append("drtio_transceiver") # same here - figure out the relations # self.sync += disable_cdr_clk_ibuf.eq( @@ -429,11 +430,18 @@ class GenericSatellite(SoCCore): self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) self.csr_devices.append("rtio_dma") + self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) + self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) + self.submodules.cri_con = rtio.CRIInterconnectShared( - [self.rtio.cri, self.rtio_dma.cri], - [self.rtio_core.cri]) + [self.drtiosat.cri], + [self.local_io.cri] + self.drtio_cri, + mode="sync", enable_routing=True) self.csr_devices.append("cri_con") + self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) + self.csr_devices.append("routing_table") + self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels) self.csr_devices.append("rtio_moninj") @@ -441,6 +449,9 @@ class GenericSatellite(SoCCore): self.ps7.s_axi_hp1) self.csr_devices.append("rtio_analyzer") + rtio_clk_period = 1e9/rtio_clk_freq + self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) + self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("cdr_clk"), rx_synchronizer=self.rx_synchronizer, @@ -452,13 +463,24 @@ class GenericSatellite(SoCCore): self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None + gtx = self.drtio_transceiver.gtps[0] + platform.add_period_constraint(gtx.txoutclk, rtio_clk_period) + platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + gtx.txoutclk, gtx.rxoutclk) + for gtx in self.drtio_transceiver.gtxs[1:]: + platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, gtx.rxoutclk) + if has_grabber: self.rustc_cfg["has_grabber"] = None self.add_csr_group("grabber", self.grabber_csr_group) for grabber in self.grabber_csr_group: self.platform.add_false_path_constraints( self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk) - + def write_csr_file(soc, filename):