cleanup, less unnecessary comments and dup code

default.nix

@@ -38,7 +38,6 @@ let
         make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
       '';
 
-      # there's probably a better way to go around it
       installPhase = ''
         mkdir -p $out $out/nix-support
         cp ../build/${fwtype}.bin $out/${fwtype}.bin

src/gateware/aux_controller.py

@@ -8,15 +8,22 @@ from migen_axi.interconnect import axi
 
 max_packet = 1024
 
-
+class _DRTIOAuxControllerBase(Module):
-# TODO: FullMemoryWE should be applied by migen.build
-@FullMemoryWE()
-class DRTIOAuxControllerAxi(Module):
     def __init__(self, link_layer):
         self.bus = axi.Interface()
         self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
         self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
 
+    def get_csrs(self):
+        return self.transmitter.get_csrs() + self.receiver.get_csrs()
+
+
+# TODO: FullMemoryWE should be applied by migen.build
+@FullMemoryWE()
+class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
+    def __init__(self, link_layer):
+        _DRTIOAuxControllerBase.__init__(self, link_layer)
+
         tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
         rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
         aw_decoder = axi.AddressDecoder(self.bus.aw,
@@ -63,21 +70,11 @@ class DRTIOAuxControllerAxi(Module):
 
         self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
 
-    def get_csrs(self):
-        return self.transmitter.get_csrs() + self.receiver.get_csrs()
 
 @FullMemoryWE()
 class DRTIOAuxControllerBare(Module):
     # Barebones version of the AuxController. No SRAM, no decoders.
     # add memories manually from tx and rx in target code.
-    def __init__(self, link_layer):
-        self.bus = axi.Interface()
-        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
-        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
-
-    def get_csrs(self):
-        return self.transmitter.get_csrs() + self.receiver.get_csrs()
-
     def get_tx_port(self):
         return self.transmitter.mem.get_port(write_capable=True)
 

src/gateware/kasli_soc.py

@@ -231,7 +231,7 @@ class GenericMaster(SoCCore):
         data_pads = [platform.request("sfp", i) for i in range(4)]
 
         self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("clk125_gtp"),  # referred to as clk gtp in schematics, but for gtx?
+            clock_pads=platform.request("clk125_gtp"),
             pads=data_pads,
             sys_clk_freq=sys_clk_freq)
         self.csr_devices.append("drtio_transceiver")
@@ -285,7 +285,6 @@ class GenericMaster(SoCCore):
 
             size = coreaux.get_mem_size()
             memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
-            # rcv in upper half of the memory, thus added second
             self.axi2csr.register_port(coreaux.get_rx_port(), size)
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
         self.rustc_cfg["has_drtio"] = None
@@ -363,7 +362,7 @@ class GenericSatellite(SoCCore):
         data_pads = [platform.request("sfp", i) for i in range(4)]
         
         self.submodules.drtio_transceiver = gtx_7series.GTX(
-            clock_pads=platform.request("clk125_gtp"),  # referred to as clk gtp in schematics, but for gtx?
+            clock_pads=platform.request("clk125_gtp"),  
             pads=data_pads,
             sys_clk_freq=sys_clk_freq)
         self.csr_devices.append("drtio_transceiver")
@@ -382,9 +381,7 @@ class GenericSatellite(SoCCore):
         self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
         self.rtio_channels.append(rtio.LogChannel())
 
-        # TSC is set to "sync" not "async" in SatelliteBase
         self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
-        # there is also no core
 
         drtioaux_csr_group = []
         drtioaux_memory_group = []

src/gateware/zc706.py

@@ -130,23 +130,28 @@ si5324_fmc33 = [
 ]
 
 
+def prepare_zc706_platform(platform):
+    platform.toolchain.bitstream_commands.extend([
+        "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+    ])
+    platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
+    platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
+    return platform
+
+
 class ZC706(SoCCore):
     def __init__(self, acpki=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
         platform = zc706.Platform()
-        platform.toolchain.bitstream_commands.extend([
+        platform = prepare_zc706_platform(platform)
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+
-        ])
         ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
 
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
         self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
         self.csr_devices.append("rtio_crg")
         self.rustc_cfg["has_rtio_crg_clock_sel"] = None
@@ -194,9 +199,7 @@ class _MasterBase(SoCCore):
         self.rustc_cfg = dict()
 
         platform = zc706.Platform()
-        platform.toolchain.bitstream_commands.extend([
+        platform = prepare_zc706_platform(platform)
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
         ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
@@ -334,20 +337,14 @@ class _SatelliteBase(SoCCore):
         self.rustc_cfg = dict()
 
         platform = zc706.Platform()
-        platform.toolchain.bitstream_commands.extend([
+        platform = prepare_zc706_platform(platform)
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
         ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
 
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
         if use_si5324_33:
             platform.add_extension(si5324_fmc33)
-        # init end
 
         self.sys_clk_freq = 125e6
         platform = self.platform
@@ -358,7 +355,6 @@ class _SatelliteBase(SoCCore):
             platform.request("sfp")
         ]
 
-        # used by sattelite objects
         self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
 
         # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
@@ -403,7 +399,7 @@ class _SatelliteBase(SoCCore):
             # manually, because software refers to rx/tx by halves of entire memory block, not names
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
         self.rustc_cfg["has_drtio"] = None
-        # it does not have drtio routing support!
+        # no repeaters - it does not have drtio routing support
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
@@ -447,8 +443,6 @@ class _SatelliteBase(SoCCore):
         fix_serdes_timing_path(self.platform)
 
     def add_rtio(self, rtio_channels):
-        # few changes from base add_rtio - moved tsc, no core
-
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
 

src/libboard_artiq/src/lib.rs

@@ -24,7 +24,6 @@ pub mod si5324;
 pub mod drtioaux;
 #[cfg(has_drtio)]
 pub mod drtioaux_async;
-#[cfg(has_drtio)]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
 

src/satman/src/main.rs

@@ -286,21 +286,21 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
         drtioaux::Packet::SpiSetConfigRequest { destination: _destination, busno: _busno, 
                                                 flags: _flags, length: _length, div: _div, cs: _cs } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when SPI is available
+            // todo: reimplement when/if SPI is available
             //let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
             drtioaux::send(0,
-                &drtioaux::Packet::SpiBasicReply { succeeded: false})
+                &drtioaux::Packet::SpiBasicReply { succeeded: false })
         },
         drtioaux::Packet::SpiWriteRequest { destination: _destination, busno: _busno, data: _data } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when SPI is available
+            // todo: reimplement when/if SPI is available
             //let succeeded = spi::write(busno, data).is_ok();
             drtioaux::send(0,
                 &drtioaux::Packet::SpiBasicReply { succeeded: false })
         }
         drtioaux::Packet::SpiReadRequest { destination: _destination, busno: _busno } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
-            // todo: reimplement when SPI is available
+            // todo: reimplement when/if SPI is available
             // match spi::read(busno) {
             //     Ok(data) => drtioaux::send(0,
             //         &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
@@ -430,7 +430,6 @@ pub extern fn main_core0() -> i32 {
     let buffer_logger = unsafe {
         logger::BufferLogger::new(&mut LOG_BUFFER[..])
     };
-    //probably will have to copy init_gateware() from runtime here too
     buffer_logger.set_uart_log_level(log::LevelFilter::Info);
     buffer_logger.register();
     log::set_max_level(log::LevelFilter::Info);
@@ -445,7 +444,6 @@ pub extern fn main_core0() -> i32 {
     let mut i2c = I2c::i2c0();
     i2c.init().expect("I2C initialization failed");
 
-    //this part was commented in runtime
     #[cfg(has_si5324)]
     si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
 
@@ -623,8 +621,6 @@ extern "C" {
     static __exidx_end: u32;
 }
 
-
-/// Called by llvm_libunwind
 #[no_mangle]
 extern fn dl_unwind_find_exidx(_pc: *const u32, len_ptr: *mut u32) -> *const u32 {
     let length;