diff --git a/src/libboard_artiq/src/drtioaux.rs b/src/libboard_artiq/src/drtioaux.rs
index 776eb8da..8d3a7a95 100644
--- a/src/libboard_artiq/src/drtioaux.rs
+++ b/src/libboard_artiq/src/drtioaux.rs
@@ -58,7 +58,7 @@ pub fn has_rx_error(linkno: u8) -> bool {
     }
 }
 
-fn copy_with_swap(src: *mut u8, dst: *mut u8, len: isize) {
+pub fn copy_with_swap(src: *mut u8, dst: *mut u8, len: isize) {
     // for some reason, everything except checksum arrives
     // with byte order swapped. and it must be sent as such too.
     unsafe {
diff --git a/src/libboard_artiq/src/drtioaux_async.rs b/src/libboard_artiq/src/drtioaux_async.rs
index 9a789a6b..eb7f219a 100644
--- a/src/libboard_artiq/src/drtioaux_async.rs
+++ b/src/libboard_artiq/src/drtioaux_async.rs
@@ -10,7 +10,7 @@ use libasync::{task, block_async};
 use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
 use crate::mem::mem::DRTIOAUX_MEM;
 use crate::pl::csr::DRTIOAUX;
-use crate::drtioaux::{Error, has_rx_error};
+use crate::drtioaux::{Error, has_rx_error, copy_with_swap};
 
 pub use crate::drtioaux_proto::Packet;
 
@@ -36,23 +36,6 @@ fn tx_ready(linkno: usize) -> nb::Result<(), Void> {
     }
 }
 
-async fn copy_with_swap(src: *mut u8, dst: *mut u8, len: isize) {
-    unsafe {
-        for i in (0..(len-4)).step_by(4) {
-            *dst.offset(i) = *src.offset(i+3);
-            *dst.offset(i+1) = *src.offset(i+2);
-            *dst.offset(i+2) = *src.offset(i+1);
-            *dst.offset(i+3) = *src.offset(i);
-        }
-        // checksum untouched
-        // unrolled for performance
-        *dst.offset(len-4) = *src.offset(len-4);
-        *dst.offset(len-3) = *src.offset(len-3);
-        *dst.offset(len-2) = *src.offset(len-2);
-        *dst.offset(len-1) = *src.offset(len-1);
-    }
-}
-
 async fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
     where F: FnOnce(&[u8]) -> Result<T, Error>
 {
@@ -63,7 +46,7 @@ async fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
             let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
             // work buffer, as byte order will need to be swapped, cannot be in place
             let mut buf: [u8; 1024] = [0; 1024];
-            copy_with_swap(ptr, buf.as_mut_ptr(), len as isize).await;
+            copy_with_swap(ptr, buf.as_mut_ptr(), len as isize);
             let result = f(&buf[0..len]);
             (DRTIOAUX[linkidx].aux_rx_present_write)(1);
             Ok(Some(result?))
@@ -104,8 +87,8 @@ pub async fn recv_timeout(linkno: u8, timeout_ms: Option<u64>,
     let limit = timer.get_time() + timeout_ms;
     let mut would_block = false;
     while timer.get_time() < limit {
-        // to ensure one last time recv would run one last time in case
-        // async would return after timeout
+        // to ensure one last time recv would run one last time
+        // in case async would return after timeout
         if would_block {
             task::r#yield().await;
         }
@@ -128,7 +111,7 @@ async fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
         // work buffer, works with unaligned mem access
         let mut buf: [u8; 1024] = [0; 1024]; 
         let len = f(&mut buf[0..len])?;
-        copy_with_swap(buf.as_mut_ptr(), ptr, len as isize).await;
+        copy_with_swap(buf.as_mut_ptr(), ptr, len as isize);
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())
diff --git a/src/libboard_artiq/src/si5324.rs b/src/libboard_artiq/src/si5324.rs
index e3eb5ed0..c083faec 100644
--- a/src/libboard_artiq/src/si5324.rs
+++ b/src/libboard_artiq/src/si5324.rs
@@ -281,7 +281,7 @@ pub fn select_input(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Res
 #[cfg(has_siphaser)]
 pub mod siphaser {
     use super::*;
-    use pl::csr;
+    use crate::pl::csr;
 
     pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: &mut GlobalTimer) -> Result<()> {
         let val = read(i2c, 3)?;