forked from M-Labs/artiq-zynq
moved si5324, added notes on required porting
This commit is contained in:
parent
60a8861a22
commit
2647ef7249
@ -7,4 +7,6 @@ authors = ["M-Labs"]
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name = "board_artiqzync"
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[dependencies]
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io = { path = "../libio", features = ["byteorder"] }
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log = "0.4"
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io = { path = "../libio", features = ["byteorder"] }
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
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@ -1,6 +1,7 @@
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use board_misoc::config; // <- port
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use board_misoc::config; // <- port; use libconfig?
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#[cfg(has_drtio_routing)]
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use board_misoc::csr; // <- port
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use pl::csr; // <- port
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use core::fmt;
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#[cfg(has_drtio_routing)]
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@ -107,6 +107,7 @@ pub fn recv(linkno: u8) -> Result<Option<Packet>, Error<!>> {
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pub fn recv_timeout(linkno: u8, timeout_ms: Option<u64>) -> Result<Packet, Error<!>> {
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let timeout_ms = timeout_ms.unwrap_or(10);
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// only place with clock
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let limit = clock::get_ms() + timeout_ms;
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while clock::get_ms() < limit {
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match recv(linkno)? {
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@ -1,5 +1,9 @@
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pub mod clock;
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#[path = "../../../build/pl.rs"]
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pub mod pl;
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#[cfg(has_drtio)]
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pub mod drtioaux;
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pub mod drtio_routing;
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pub mod si5324;
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@ -1,158 +0,0 @@
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use core::str::Utf8Error;
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use byteorder::{ByteOrder, NativeEndian};
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use alloc::vec;
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use alloc::string::String;
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use core_io::{Read, Write, Error as IoError};
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#[allow(dead_code)]
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#[derive(Debug, Clone, PartialEq)]
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pub enum ReadStringError<T> {
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Utf8(Utf8Error),
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Other(T)
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}
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pub trait ProtoRead {
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type ReadError;
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fn read_exact(&mut self, buf: &mut [u8]) -> Result<(), Self::ReadError>;
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#[inline]
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fn read_u8(&mut self) -> Result<u8, Self::ReadError> {
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let mut bytes = [0; 1];
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self.read_exact(&mut bytes)?;
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Ok(bytes[0])
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}
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#[inline]
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fn read_u16(&mut self) -> Result<u16, Self::ReadError> {
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let mut bytes = [0; 2];
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self.read_exact(&mut bytes)?;
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Ok(NativeEndian::read_u16(&bytes))
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}
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#[inline]
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fn read_u32(&mut self) -> Result<u32, Self::ReadError> {
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let mut bytes = [0; 4];
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self.read_exact(&mut bytes)?;
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Ok(NativeEndian::read_u32(&bytes))
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}
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#[inline]
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fn read_u64(&mut self) -> Result<u64, Self::ReadError> {
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let mut bytes = [0; 8];
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self.read_exact(&mut bytes)?;
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Ok(NativeEndian::read_u64(&bytes))
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}
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#[inline]
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fn read_bool(&mut self) -> Result<bool, Self::ReadError> {
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Ok(self.read_u8()? != 0)
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}
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#[inline]
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fn read_bytes(&mut self) -> Result<::alloc::vec::Vec<u8>, Self::ReadError> {
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let length = self.read_u32()?;
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let mut value = vec![0; length as usize];
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self.read_exact(&mut value)?;
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Ok(value)
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}
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#[inline]
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fn read_string(&mut self) -> Result<::alloc::string::String, ReadStringError<Self::ReadError>> {
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let bytes = self.read_bytes().map_err(ReadStringError::Other)?;
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String::from_utf8(bytes).map_err(|err| ReadStringError::Utf8(err.utf8_error()))
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}
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}
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pub trait ProtoWrite {
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type WriteError;
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fn write_all(&mut self, buf: &[u8]) -> Result<(), Self::WriteError>;
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#[inline]
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fn write_u8(&mut self, value: u8) -> Result<(), Self::WriteError> {
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let bytes = [value; 1];
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self.write_all(&bytes)
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}
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#[inline]
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fn write_i8(&mut self, value: i8) -> Result<(), Self::WriteError> {
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let bytes = [value as u8; 1];
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self.write_all(&bytes)
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}
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#[inline]
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fn write_u16(&mut self, value: u16) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 2];
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NativeEndian::write_u16(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_i16(&mut self, value: i16) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 2];
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NativeEndian::write_i16(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_u32(&mut self, value: u32) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 4];
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NativeEndian::write_u32(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_i32(&mut self, value: i32) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 4];
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NativeEndian::write_i32(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_u64(&mut self, value: u64) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 8];
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NativeEndian::write_u64(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_i64(&mut self, value: i64) -> Result<(), Self::WriteError> {
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let mut bytes = [0; 8];
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NativeEndian::write_i64(&mut bytes, value);
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self.write_all(&bytes)
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}
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#[inline]
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fn write_bool(&mut self, value: bool) -> Result<(), Self::WriteError> {
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self.write_u8(value as u8)
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}
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#[inline]
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fn write_bytes(&mut self, value: &[u8]) -> Result<(), Self::WriteError> {
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self.write_u32(value.len() as u32)?;
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self.write_all(value)
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}
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#[inline]
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fn write_string(&mut self, value: &str) -> Result<(), Self::WriteError> {
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self.write_bytes(value.as_bytes())
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}
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}
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impl<T> ProtoRead for T where T: Read + ?Sized {
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type ReadError = IoError;
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fn read_exact(&mut self, buf: &mut [u8]) -> Result<(), Self::ReadError> {
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T::read_exact(self, buf)
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}
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}
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impl<T> ProtoWrite for T where T: Write + ?Sized {
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type WriteError = IoError;
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fn write_all(&mut self, buf: &[u8]) -> Result<(), Self::WriteError> {
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T::write_all(self, buf)
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}
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}
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258
src/libboard_artiqzynq/si5324.rs
Normal file
258
src/libboard_artiqzynq/si5324.rs
Normal file
@ -0,0 +1,258 @@
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use core::result;
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use log::info;
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use libboard_zynq::i2c::I2c;
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type Result<T> = result::Result<T, &'static str>;
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const ADDRESS: u8 = 0x68;
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// NOTE: the logical parameters DO NOT MAP to physical values written
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// into registers. They have to be mapped; see the datasheet.
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// DSPLLsim reports the logical parameters in the design summary, not
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// the physical register values.
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pub struct FrequencySettings {
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pub n1_hs: u8,
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pub nc1_ls: u32,
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pub n2_hs: u8,
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pub n2_ls: u32,
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pub n31: u32,
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pub n32: u32,
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pub bwsel: u8,
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pub crystal_ref: bool
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}
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pub enum Input {
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Ckin1,
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Ckin2,
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}
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fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
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if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
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return Err("NC1_LS must be 0 or even")
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}
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if settings.nc1_ls > (1 << 20) {
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return Err("NC1_LS is too high")
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}
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if (settings.n2_ls % 2) == 1 {
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return Err("N2_LS must be even")
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}
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if settings.n2_ls > (1 << 20) {
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return Err("N2_LS is too high")
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}
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if settings.n31 > (1 << 19) {
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return Err("N31 is too high")
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}
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if settings.n32 > (1 << 19) {
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return Err("N32 is too high")
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}
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let r = FrequencySettings {
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n1_hs: match settings.n1_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N1_HS has an invalid value")
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},
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nc1_ls: settings.nc1_ls - 1,
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n2_hs: match settings.n2_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N2_HS has an invalid value")
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},
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n2_ls: settings.n2_ls - 1,
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n31: settings.n31 - 1,
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n32: settings.n32 - 1,
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bwsel: settings.bwsel,
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crystal_ref: settings.crystal_ref
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};
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Ok(r)
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}
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fn write(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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if !i2c.write(val).unwrap() {
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return Err("Si5324 failed to ack value")
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}
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i2c.stop().unwrap();
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Ok(())
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}
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fn write_no_ack_value(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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i2c.write(val).unwrap();
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i2c.stop().unwrap();
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Ok(())
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}
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fn read(i2c: &mut I2c, reg: u8) -> Result<u8> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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i2c.restart().unwrap();
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if !i2c.write((ADDRESS << 1) | 1).unwrap() {
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return Err("Si5324 failed to ack read address")
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}
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let val = i2c.read(false).unwrap();
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i2c.stop().unwrap();
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Ok(val)
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}
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fn rmw<F>(i2c: &mut I2c, reg: u8, f: F) -> Result<()> where
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F: Fn(u8) -> u8 {
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let value = read(i2c, reg)?;
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write(i2c, reg, f(value))?;
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Ok(())
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}
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fn ident(i2c: &mut I2c) -> Result<u16> {
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Ok(((read(i2c, 134)? as u16) << 8) | (read(i2c, 135)? as u16))
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}
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fn soft_reset(i2c: &mut I2c) -> Result<()> {
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//TODO write_no_ack_value(i2c, 136, read(136)? | 0x80)?;
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//TODO clock::spin_us(10_000);
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Ok(())
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}
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fn has_xtal(i2c: &mut I2c) -> Result<bool> {
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Ok((read(i2c, 129)? & 0x01) == 0) // LOSX_INT=0
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}
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fn has_ckin(i2c: &mut I2c, input: Input) -> Result<bool> {
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match input {
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Input::Ckin1 => Ok((read(i2c, 129)? & 0x02) == 0), // LOS1_INT=0
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Input::Ckin2 => Ok((read(i2c, 129)? & 0x04) == 0), // LOS2_INT=0
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}
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}
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fn locked(i2c: &mut I2c) -> Result<bool> {
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Ok((read(i2c, 130)? & 0x01) == 0) // LOL_INT=0
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}
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fn monitor_lock(i2c: &mut I2c) -> Result<()> {
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info!("waiting for Si5324 lock...");
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// TODO let t = clock::get_ms();
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while !locked(i2c)? {
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// Yes, lock can be really slow.
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/*if clock::get_ms() > t + 20000 {
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return Err("Si5324 lock timeout");
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}*/
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}
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info!(" ...locked");
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Ok(())
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}
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fn init(i2c: &mut I2c) -> Result<()> {
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info!("init test");
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#[cfg(feature = "target_kasli_soc")]
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{
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i2c.pca9548_select(0x70, 0)?;
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i2c.pca9548_select(0x71, 1 << 3)?;
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}
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if ident(i2c)? != 0x0182 {
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return Err("Si5324 does not have expected product number");
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}
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soft_reset(i2c)?;
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Ok(())
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}
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pub fn bypass(i2c: &mut I2c, input: Input) -> Result<()> {
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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init(i2c)?;
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rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
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rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?; // CKSEL_REG
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rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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rmw(i2c, 0, |v| (v & 0xfd) | 0x02)?; // BYPASS_REG=1
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Ok(())
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}
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pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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init(i2c)?;
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if settings.crystal_ref {
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rmw(i2c, 0, |v| v | 0x40)?; // FREE_RUN=1
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}
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rmw(i2c, 2, |v| (v & 0x0f) | (s.bwsel << 4))?;
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rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
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rmw(i2c, 3, |v| (v & 0x2f) | (cksel_reg << 6) | 0x10)?; // CKSEL_REG, SQ_ICAL=1
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rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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write(i2c, 25, (s.n1_hs << 5 ) as u8)?;
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write(i2c, 31, (s.nc1_ls >> 16) as u8)?;
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write(i2c, 32, (s.nc1_ls >> 8 ) as u8)?;
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write(i2c, 33, (s.nc1_ls) as u8)?;
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write(i2c, 34, (s.nc1_ls >> 16) as u8)?; // write to NC2_LS as well
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write(i2c, 35, (s.nc1_ls >> 8 ) as u8)?;
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write(i2c, 36, (s.nc1_ls) as u8)?;
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write(i2c, 40, (s.n2_hs << 5 ) as u8 | (s.n2_ls >> 16) as u8)?;
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write(i2c, 41, (s.n2_ls >> 8 ) as u8)?;
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write(i2c, 42, (s.n2_ls) as u8)?;
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write(i2c, 43, (s.n31 >> 16) as u8)?;
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write(i2c, 44, (s.n31 >> 8) as u8)?;
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write(i2c, 45, (s.n31) as u8)?;
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write(i2c, 46, (s.n32 >> 16) as u8)?;
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write(i2c, 47, (s.n32 >> 8) as u8)?;
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write(i2c, 48, (s.n32) as u8)?;
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rmw(i2c, 137, |v| v | 0x01)?; // FASTLOCK=1
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rmw(i2c, 136, |v| v | 0x40)?; // ICAL=1
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if !has_xtal(i2c)? {
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return Err("Si5324 misses XA/XB signal");
|
||||
}
|
||||
if !has_ckin(i2c, input)? {
|
||||
return Err("Si5324 misses clock input signal");
|
||||
}
|
||||
|
||||
monitor_lock(i2c)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn select_input(i2c: &mut I2c, input: Input) -> Result<()> {
|
||||
let cksel_reg = match input {
|
||||
Input::Ckin1 => 0b00,
|
||||
Input::Ckin2 => 0b01,
|
||||
};
|
||||
rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?;
|
||||
if !has_ckin(i2c, input)? {
|
||||
return Err("Si5324 misses clock input signal");
|
||||
}
|
||||
monitor_lock(i2c)?;
|
||||
Ok(())
|
||||
}
|
||||
@ -7,13 +7,11 @@ extern crate log;
|
||||
use core::convert::TryFrom;
|
||||
use board_misoc::{csr, irq, ident, clock, uart_logger, i2c}; // <- port, use libboard_zynq
|
||||
#[cfg(has_si5324)]
|
||||
use board_artiq::si5324; // <- move from runtime
|
||||
use board_artiqzynq::si5324; // <- move from runtime
|
||||
#[cfg(has_wrpll)]
|
||||
use board_artiq::wrpll; // <- port
|
||||
use board_artiq::{spi, drtioaux}; // <- port, use libboard_zynq
|
||||
use board_artiq::drtio_routing; // <- artiqzync
|
||||
#[cfg(has_hmc830_7043)]
|
||||
use board_artiq::hmc830_7043; // <- port?
|
||||
|
||||
mod repeater;
|
||||
#[cfg(has_jdcg)]
|
||||
@ -296,35 +294,6 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
|
||||
drtioaux::Packet::JdacBasicRequest { destination: _destination, dacno: _dacno,
|
||||
reqno: _reqno, param: _param } => {
|
||||
forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
|
||||
#[cfg(has_ad9154)]
|
||||
let (succeeded, retval) = {
|
||||
#[cfg(rtio_frequency = "125.0")]
|
||||
const LINERATE: u64 = 5_000_000_000;
|
||||
#[cfg(rtio_frequency = "150.0")]
|
||||
const LINERATE: u64 = 6_000_000_000;
|
||||
match _reqno {
|
||||
jdac_common::INIT => (board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(), 0),
|
||||
jdac_common::PRINT_STATUS => { board_artiq::ad9154::status(_dacno); (true, 0) },
|
||||
jdac_common::PRBS => (board_artiq::ad9154::prbs(_dacno).is_ok(), 0),
|
||||
jdac_common::STPL => (board_artiq::ad9154::stpl(_dacno, 4, 2).is_ok(), 0),
|
||||
jdac_common::SYSREF_DELAY_DAC => { board_artiq::hmc830_7043::hmc7043::sysref_delay_dac(_dacno, _param); (true, 0) },
|
||||
jdac_common::SYSREF_SLIP => { board_artiq::hmc830_7043::hmc7043::sysref_slip(); (true, 0) },
|
||||
jdac_common::SYNC => {
|
||||
match board_artiq::ad9154::sync(_dacno) {
|
||||
Ok(false) => (true, 0),
|
||||
Ok(true) => (true, 1),
|
||||
Err(e) => {
|
||||
error!("DAC sync failed: {}", e);
|
||||
(false, 0)
|
||||
}
|
||||
}
|
||||
},
|
||||
jdac_common::DDMTD_SYSREF_RAW => (true, jdac_common::measure_ddmdt_phase_raw() as u8),
|
||||
jdac_common::DDMTD_SYSREF => (true, jdac_common::measure_ddmdt_phase() as u8),
|
||||
_ => (false, 0)
|
||||
}
|
||||
};
|
||||
#[cfg(not(has_ad9154))]
|
||||
let (succeeded, retval) = (false, 0);
|
||||
drtioaux::send(0,
|
||||
&drtioaux::Packet::JdacBasicReply { succeeded: succeeded, retval: retval })
|
||||
@ -503,17 +472,6 @@ pub extern fn main() -> i32 {
|
||||
wrpll::diagnostics();
|
||||
init_rtio_crg();
|
||||
|
||||
#[cfg(has_hmc830_7043)]
|
||||
/* must be the first SPI init because of HMC830 SPI mode selection */
|
||||
hmc830_7043::init().expect("cannot initialize HMC830/7043");
|
||||
#[cfg(has_ad9154)]
|
||||
{
|
||||
jdac_common::init_ddmtd().expect("failed to initialize SYSREF DDMTD core");
|
||||
for dacno in 0..csr::CONFIG_AD9154_COUNT {
|
||||
board_artiq::ad9154::reset_and_detect(dacno as u8).expect("AD9154 DAC not detected");
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(has_drtio_routing)]
|
||||
let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
|
||||
#[cfg(not(has_drtio_routing))]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user