forked from M-Labs/artiq-zynq
gateware: fixed cfg keys - case consistent w/ code
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parent
5e916f588e
commit
20681a13c4
@ -264,8 +264,8 @@ class GenericMaster(SoCCore):
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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@ -406,8 +406,8 @@ class GenericSatellite(SoCCore):
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.config["has_drtio"] = None
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self.config["has_drtio_routing"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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@ -447,7 +447,7 @@ class GenericSatellite(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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@ -457,8 +457,9 @@ class GenericSatellite(SoCCore):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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gtx = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtx.txoutclk, rtio_clk_period)
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@ -327,8 +327,8 @@ class Master(SoCCore):
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.config["has_drtio"] = None
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self.config["has_drtio_routing"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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@ -336,8 +336,8 @@ class Master(SoCCore):
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self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_as_synthesizer"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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