From 20681a13c4897aa7943a9f4f0549e2af869b70dd Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 6 Sep 2021 10:57:42 +0200 Subject: [PATCH] gateware: fixed cfg keys - case consistent w/ code --- src/gateware/kasli_soc.py | 15 ++++++++------- src/gateware/zc706.py | 8 ++++---- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 2133f02b..d952ea73 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -264,8 +264,8 @@ class GenericMaster(SoCCore): memory_address = self.mem_map["drtioaux"] + 0x800*i self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) - self.config["HAS_DRTIO"] = None - self.config["HAS_DRTIO_ROUTING"] = None + self.rustc_cfg["has_drtio"] = None + self.rustc_cfg["has_drtio_routing"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) @@ -406,8 +406,8 @@ class GenericSatellite(SoCCore): memory_address = self.mem_map["drtioaux"] + 0x800*i self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) - self.config["HAS_DRTIO"] = None - self.config["HAS_DRTIO_ROUTING"] = None + self.config["has_drtio"] = None + self.config["has_drtio_routing"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) @@ -447,7 +447,7 @@ class GenericSatellite(SoCCore): self.csr_devices.append("rtio_analyzer") rtio_clk_period = 1e9/rtio_clk_freq - self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) + self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("cdr_clk"), @@ -457,8 +457,9 @@ class GenericSatellite(SoCCore): platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") - self.config["HAS_SI5324"] = None - self.config["SI5324_SOFT_RESET"] = None + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["has_siphaser"] = None + self.rustc_cfg["si5324_soft_reset"] = None gtx = self.drtio_transceiver.gtps[0] platform.add_period_constraint(gtx.txoutclk, rtio_clk_period) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index a60d72d4..e869f2e7 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -327,8 +327,8 @@ class Master(SoCCore): memory_address = self.mem_map["drtioaux"] + 0x800*i self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) - self.config["HAS_DRTIO"] = None - self.config["HAS_DRTIO_ROUTING"] = None + self.config["has_drtio"] = None + self.config["has_drtio_routing"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) @@ -336,8 +336,8 @@ class Master(SoCCore): self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") - self.config["HAS_SI5324"] = None - self.config["SI5324_AS_SYNTHESIZER"] = None + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_as_synthesizer"] = None rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel