From 1ccae0d442e1cff1eaf2985b65b75e1e5bc31215 Mon Sep 17 00:00:00 2001 From: morgan Date: Mon, 11 Sep 2023 11:15:55 +0800 Subject: [PATCH] consolidate all `write..file()` into `config.py` --- src/gateware/config.py | 22 ++++++++++++++++++++++ src/gateware/kasli_soc.py | 28 +--------------------------- src/gateware/zc706.py | 27 +-------------------------- 3 files changed, 24 insertions(+), 53 deletions(-) create mode 100644 src/gateware/config.py diff --git a/src/gateware/config.py b/src/gateware/config.py new file mode 100644 index 00000000..10150dfc --- /dev/null +++ b/src/gateware/config.py @@ -0,0 +1,22 @@ +from misoc.integration import cpu_interface + +def write_csr_file(soc, filename): + with open(filename, "w") as f: + f.write(cpu_interface.get_csr_rust( + soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) + +def write_mem_file(soc, filename): + with open(filename, "w") as f: + f.write(cpu_interface.get_mem_rust( + soc.get_memory_regions(), soc.get_memory_groups(), None)) + +def write_rustc_cfg_file(soc, filename): + with open(filename, "w") as f: + for name, origin, busword, obj in soc.get_csr_regions(): + f.write("has_{}\n".format(name.lower())) + for name, value in soc.get_constants(): + if name.upper().startswith("CONFIG_"): + if value is None: + f.write("{}\n".format(name.lower()[7:])) + else: + f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 3cce2296..2a3c0cb5 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore from migen_axi.platforms import kasli_soc from misoc.interconnect.csr import * from misoc.cores import virtual_leds -from misoc.integration import cpu_interface from artiq.coredevice import jsondesc from artiq.gateware import rtio, eem_7series @@ -27,7 +26,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking - +from config import write_csr_file, write_mem_file, write_rustc_cfg_file eem_iostandard_dict = { 0: "LVDS_25", @@ -484,31 +483,6 @@ class GenericSatellite(SoCCore): self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready) for i, channel in enumerate(self.gt_drtio.channels)] - -def write_mem_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_mem_rust( - soc.get_memory_regions(), soc.get_memory_groups(), None)) - - -def write_csr_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_csr_rust( - soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) - - -def write_rustc_cfg_file(soc, filename): - with open(filename, "w") as f: - for name, origin, busword, obj in soc.get_csr_regions(): - f.write("has_{}\n".format(name.lower())) - for name, value in soc.get_constants(): - if name.upper().startswith("CONFIG_"): - if value is None: - f.write("{}\n".format(name.lower()[7:])) - else: - f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) - - def main(): parser = argparse.ArgumentParser( description="ARTIQ device binary builder for generic Kasli-SoC systems") diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index e770633c..6ae46b41 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -10,7 +10,6 @@ from migen.genlib.cdc import MultiReg from migen_axi.integration.soc_core import SoCCore from migen_axi.platforms import zc706 from misoc.interconnect.csr import * -from misoc.integration import cpu_interface from misoc.cores import gpio from artiq.gateware import rtio, nist_clock, nist_qc2 @@ -26,7 +25,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking - +from config import write_csr_file, write_mem_file, write_rustc_cfg_file class SMAClkinForward(Module): def __init__(self, platform): @@ -672,30 +671,6 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} - -def write_csr_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_csr_rust( - soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) - -def write_mem_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_mem_rust( - soc.get_memory_regions(), soc.get_memory_groups(), None)) - - -def write_rustc_cfg_file(soc, filename): - with open(filename, "w") as f: - for name, origin, busword, obj in soc.get_csr_regions(): - f.write("has_{}\n".format(name.lower())) - for name, value in soc.get_constants(): - if name.upper().startswith("CONFIG_"): - if value is None: - f.write("{}\n".format(name.lower()[7:])) - else: - f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) - - def main(): parser = argparse.ArgumentParser( description="ARTIQ port to the ZC706 Zynq development kit")