diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index d952ea73..45eb1e0c 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
 import dma
 import analyzer
 import acpki
-
+import aux_controller
 
 class RTIOCRG(Module, AutoCSR):
     def __init__(self, platform):
@@ -258,7 +258,7 @@ class GenericMaster(SoCCore):
             self.drtio_cri.append(core.cri)
             self.csr_devices.append(core_name)
 
-            coreaux = cdr(DRTIOAuxController(core.link_layer))
+            coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
             setattr(self.submodules, coreaux_name, coreaux)
             self.csr_devices.append(coreaux_name)
 
@@ -337,6 +337,11 @@ class GenericSatellite(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+
+        # todo: replace rtio_crg with rtioclockmultiplier
+
+        # put range(1) to make it work while axi doesn't support anything but P2P
         data_pads = [platform.request("sfp", i) for i in range(4)]
         
         self.submodules.drtio_transceiver = gtx_7series.GTX(
@@ -345,14 +350,6 @@ class GenericSatellite(SoCCore):
             sys_clk_freq=sys_clk_freq)
         self.csr_devices.append("drtio_transceiver")
 
-        self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOCRG(self.platform)
-        self.csr_devices.append("rtio_crg")
-        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk)
-
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
         if has_grabber:
@@ -400,7 +397,7 @@ class GenericSatellite(SoCCore):
                 self.drtio_cri.append(core.cri)
                 self.csr_devices.append(corerep_name)
 
-            coreaux = cdr(DRTIOAuxController(core.link_layer))
+            coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
             setattr(self.submodules, coreaux_name, coreaux)
             self.csr_devices.append(coreaux_name)
 
@@ -427,7 +424,7 @@ class GenericSatellite(SoCCore):
         self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
         self.csr_devices.append("rtio_dma")
 
-        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
         self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
 
         self.submodules.cri_con = rtio.CRIInterconnectShared(
@@ -442,18 +439,14 @@ class GenericSatellite(SoCCore):
         self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
         self.csr_devices.append("rtio_moninj")
 
-        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
-                                                          self.ps7.s_axi_hp1)
-        self.csr_devices.append("rtio_analyzer")
-
         rtio_clk_period = 1e9/rtio_clk_freq
         self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
 
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("cdr_clk"),
             rx_synchronizer=self.rx_synchronizer,
-            ref_clk=self.crg.clk125_div2, ref_div2=True,
-            rtio_clk_freq=rtio_clk_freq)
+            ultrascale=False,
+            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
         platform.add_false_path_constraints(
             self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
         self.csr_devices.append("siphaser")
@@ -461,12 +454,12 @@ class GenericSatellite(SoCCore):
         self.rustc_cfg["has_siphaser"] = None
         self.rustc_cfg["si5324_soft_reset"] = None
 
-        gtx = self.drtio_transceiver.gtps[0]
-        platform.add_period_constraint(gtx.txoutclk, rtio_clk_period)
-        platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
         platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
-            gtx.txoutclk, gtx.rxoutclk)
+            gtx0.txoutclk, gtx0.rxoutclk)
         for gtx in self.drtio_transceiver.gtxs[1:]:
             platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
             platform.add_false_path_constraints(
@@ -475,9 +468,7 @@ class GenericSatellite(SoCCore):
         if has_grabber:
             self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)
-            for grabber in self.grabber_csr_group:
-                self.platform.add_false_path_constraints(
-                    self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
+            # no RTIO CRG here
      
 
 def write_mem_file(soc, filename):
diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index c24bfe7e..7bdf7196 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -9,7 +9,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
-from migen_axi.interconnect import sram, axi
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
 from misoc.cores import gpio
@@ -129,7 +128,6 @@ class ZC706(SoCCore):
 
 class _MasterBase(SoCCore):
     mem_map = {
-
         "drtioaux":     0x40000000,
     }
     mem_map.update(SoCCore.mem_map)