From 1358c8bfe924c6d366c0c48607ac47055e5d279e Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 24 Aug 2021 12:01:04 +0200 Subject: [PATCH] zc706 gateware: base class for drtio is SoCCore --- src/gateware/zc706.py | 82 ++++++++++++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 29 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index ddaae026..f333e82f 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -9,6 +9,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import MultiReg from migen_axi.integration.soc_core import SoCCore from migen_axi.platforms import zc706 +from migen_axi.interconnect import sram, axi from misoc.interconnect.csr import * from misoc.integration import cpu_interface from misoc.cores import gpio @@ -26,7 +27,6 @@ import analyzer import acpki import aux_controller - class RTIOCRG(Module, AutoCSR): def __init__(self, platform, rtio_internal_clk): self.clock_sel = CSRStorage() @@ -70,7 +70,6 @@ class RTIOCRG(Module, AutoCSR): MultiReg(pll_locked, self.pll_locked.status) ] - class ZC706(SoCCore): def __init__(self, acpki=False): self.acpki = acpki @@ -259,17 +258,30 @@ class NIST_QC2(ZC706): self.add_rtio(rtio_channels) -class Master(ZC706): +class Master(SoCCore): mem_map = { - "cri_con": 0x10000000, - "rtio": 0x20000000, - "rtio_dma": 0x30000000, - "drtioaux": 0x50000000, + # "cri_con": 0x10000000, + # "rtio": 0x20000000, + # "rtio_dma": 0x30000000, + "drtioaux": 0x40000000, } mem_map.update(SoCCore.mem_map) - def __init__(self, **kwargs): - ZC706.__init__(self, **kwargs) + def __init__(self, acpki=False): + self.acpki = acpki + self.rustc_cfg = dict() + + platform = zc706.Platform() + platform.toolchain.bitstream_commands.extend([ + "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", + ]) + ident = self.__class__.__name__ + if self.acpki: + ident = "acpki_" + ident + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + + platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") + platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") sys_clk_freq = 125e6 @@ -343,6 +355,8 @@ class Master(ZC706): platform.add_false_path_constraints( self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk) + self.rtio_crg = RTIOCRG(self.platform, self.drtio_transceiver.rtio_clk_freq) + rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) @@ -354,23 +368,41 @@ class Master(ZC706): self.add_rtio(rtio_channels) -class Satellite(ZC706): +class Satellite(SoCCore): mem_map = { - "drtioaux": 0x50000000, + "drtioaux": 0x40000000, } mem_map.update(SoCCore.mem_map) - def __init__(self, **kwargs): - ZC706.__init__(self, **kwargs) - sys_clk_freq = 125e6 + def __init__(self, acpki=False): + self.acpki = acpki + self.rustc_cfg = dict() + platform = zc706.Platform() + platform.toolchain.bitstream_commands.extend([ + "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", + ]) + ident = self.__class__.__name__ + if self.acpki: + ident = "acpki_" + ident + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + + platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") + platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") + # init end + + sys_clk_freq = 125e6 platform = self.platform + # SFP self.comb += platform.request("sfp_tx_disable_n").eq(1) data_pads = [ platform.request("sfp") ] + # used by sattelite objects + self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) + # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), @@ -378,8 +410,6 @@ class Satellite(ZC706): sys_clk_freq=sys_clk_freq) self.csr_devices.append("drtio_transceiver") - self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) - drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] @@ -415,13 +445,13 @@ class Satellite(ZC706): memory_address = self.mem_map["drtioaux"] + 0x800*i self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) - self.config["HAS_DRTIO"] = None - self.config["HAS_DRTIO_ROUTING"] = None + self.rustc_cfg["has_drtio"] = None + self.rustc_cfg["has_drtio_routing"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) - self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( @@ -434,7 +464,7 @@ class Satellite(ZC706): self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") - self.config["HAS_SI5324"] = None + self.rustc_cfg["HAS_SI5324"] = None rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel @@ -465,7 +495,9 @@ class Satellite(ZC706): def add_rtio(self, rtio_channels): # few changes from base add_rtio - moved tsc, no core - self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) + + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") if self.acpki: self.rustc_cfg["ki_impl"] = "acp" @@ -489,13 +521,6 @@ class Satellite(ZC706): self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") - self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) - self.csr_devices.append("rtio_moninj") - - self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri, - self.ps7.s_axi_hp1) - self.csr_devices.append("rtio_analyzer") - VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2, Master, Satellite]} @@ -549,6 +574,5 @@ def main(): if args.g is not None: soc.build(build_dir=args.g) - if __name__ == "__main__": main()