diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 68c9ff80..d4b25cfc 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -317,7 +317,9 @@ class Master(ZC706):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
+            # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
+            # currently removed - DRTIOAuxController works with Wishbone
+            # while the board supports AXI
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtio", drtio_csr_group)
@@ -421,7 +423,9 @@ class Satellite(ZC706):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
+            # self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
+            # currently removed - DRTIOAuxController works with Wishbone
+            # while the board supports AXI
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)