From 1160676fd616fc60082f581171eee52b0535ab39 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 15 Sep 2021 11:19:43 +0200 Subject: [PATCH] zc706: changed io standard for si5324 on nist backplates --- src/gateware/zc706.py | 63 ++++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 1e599aec..5a597501 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -112,6 +112,24 @@ def fix_serdes_timing_path(platform): ) +# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply. +# This also changes the I/O standard for some on-board LEDs. +leds_fmc33 = [ + ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")), + ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")), + ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")), + ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")), +] + +# same deal as with LEDs - changed I/O standard. +si5324_fmc33 = [ + ("si5324_33", 0, + Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")), + Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33")) + ), +] + + class ZC706(SoCCore): def __init__(self, acpki=False): self.acpki = acpki @@ -169,9 +187,9 @@ class ZC706(SoCCore): self.ps7.s_axi_hp1) self.csr_devices.append("rtio_analyzer") -class _MasterBase(SoCCore): - def __init__(self, acpki=False): +class _MasterBase(SoCCore): + def __init__(self, acpki=False, use_si5324_33=False): self.acpki = acpki self.rustc_cfg = dict() @@ -187,6 +205,9 @@ class _MasterBase(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") + if use_si5324_33: + platform.add_extension(si5324_fmc33) + self.sys_clk_freq = 125e6 platform = self.platform @@ -238,7 +259,11 @@ class _MasterBase(SoCCore): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) - self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) + + if use_si5324_33: + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) + else: + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_as_synthesizer"] = None @@ -262,10 +287,8 @@ class _MasterBase(SoCCore): self.rtio_crg = RTIOCRG(self.platform, self.drtio_transceiver.rtio_clk_freq) - class _SatelliteBase(SoCCore): - - def __init__(self, acpki=False): + def __init__(self, acpki=False, use_si5324_33=False): self.acpki = acpki self.rustc_cfg = dict() @@ -280,6 +303,9 @@ class _SatelliteBase(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") + + if use_si5324_33: + platform.add_extension(si5324_fmc33) # init end self.sys_clk_freq = 125e6 @@ -351,7 +377,10 @@ class _SatelliteBase(SoCCore): platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") - self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) + if use_si5324_33: + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) + else: + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") self.rustc_cfg["has_si5324"] = None self.rustc_cfg["has_siphaser"] = None @@ -416,14 +445,6 @@ class _Simple_RTIO: self.add_rtio(rtio_channels) -# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply. -# This also changes the I/O standard for some on-board LEDs. -leds_fmc33 = [ - ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")), - ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")), - ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")), - ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")), -] class _NIST_CLOCK_RTIO: """ @@ -531,12 +552,12 @@ class Simple(ZC706, _Simple_RTIO): class Master(_MasterBase, _Simple_RTIO): def __init__(self, acpki): - _MasterBase.__init__(self, acpki) + _MasterBase.__init__(self, acpki, use_si5324_33=False) _Simple_RTIO.__init__(self) class Satellite(_SatelliteBase, _Simple_RTIO): def __init__(self, acpki): - _SatelliteBase.__init__(self, acpki) + _SatelliteBase.__init__(self, acpki, use_si5324_33=False) _Simple_RTIO.__init__(self) class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): @@ -546,7 +567,7 @@ class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): def __init__(self, acpki): - _MasterBase.__init__(self, acpki) + _MasterBase.__init__(self, acpki, use_si5324_33=True) self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(self.platform) @@ -554,7 +575,7 @@ class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): def __init__(self, acpki): - _SatelliteBase.__init__(self, acpki) + _SatelliteBase.__init__(self, acpki, use_si5324_33=True) self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(self.platform) @@ -567,7 +588,7 @@ class NIST_QC2(ZC706, _NIST_QC2_RTIO): class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): def __init__(self, acpki): - _MasterBase.__init__(self, acpki) + _MasterBase.__init__(self, acpki, use_si5324_33=True) self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(self.platform) @@ -575,7 +596,7 @@ class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): def __init__(self, acpki): - _SatelliteBase.__init__(self, acpki) + _SatelliteBase.__init__(self, acpki, use_si5324_33=True) self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(self.platform)