forked from M-Labs/zynq-rs
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2 Commits
e894f502a4
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9d076d5c24
Author | SHA1 | Date |
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Simon Renblad | 9d076d5c24 | |
Simon Renblad | 6d2c26fe73 |
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@ -26,9 +26,6 @@ interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, {
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boot_core0();
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boot_core0();
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}
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}
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1 => {
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1 => {
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while !CORE1_ENABLED.get() {
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spin_lock_yield();
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}
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boot_core1();
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boot_core1();
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}
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}
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_ => unreachable!(),
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_ => unreachable!(),
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@ -69,7 +66,8 @@ unsafe extern "C" fn boot_core1() -> ! {
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mpcore = mpcore::RegisterBlock::mpcore();
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mpcore.scu_invalidate.invalidate_core1();
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mpcore.scu_invalidate.invalidate_core1();
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let mmu_table = mmu::L1Table::get();
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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mmu::with_mmu(mmu_table, || {
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ACTLR.enable_smp();
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ACTLR.enable_smp();
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ACTLR.enable_prefetch();
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ACTLR.enable_prefetch();
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@ -128,11 +126,6 @@ impl Core1 {
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}
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}
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}
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}
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unsafe {
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CORE1_ENABLED.set(true);
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}
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// Flush cache-line
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cache::dcc(unsafe { &CORE1_ENABLED });
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if sdram {
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if sdram {
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cache::dccmvac(0);
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cache::dccmvac(0);
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asm::dsb();
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asm::dsb();
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