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zynq-rs
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base: srenblad:9d076d5c24b602666103ee10c3201276092005de
Branches Tags
srenblad:master
srenblad:bump_to_latest
srenblad:improve_tcp_stream
srenblad:change_to_core2
srenblad:up_rust_llvm_versions
srenblad:add_llvm_11
srenblad:esavkin/reboot_support
M-Labs:master
..
compare: srenblad:e894f502a45b414ec2407d49b0c75451940d6a5d
Branches Tags
srenblad:bump_to_latest
srenblad:improve_tcp_stream
srenblad:change_to_core2
srenblad:up_rust_llvm_versions
srenblad:add_llvm_11
srenblad:master
srenblad:esavkin/reboot_support
M-Labs:master

No commits in common. "9d076d5c24b602666103ee10c3201276092005de" and "e894f502a45b414ec2407d49b0c75451940d6a5d" have entirely different histories.
9d076d5c24 ... e894f502a4

1 changed files with 9 additions and 2 deletions
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11
libsupport_zynq/src/boot.rs
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@ -26,6 +26,9 @@ interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, {
boot_core0();
}
1 => {
while !CORE1_ENABLED.get() {
spin_lock_yield();
}
boot_core1();
}
_ => unreachable!(),
@ -66,8 +69,7 @@ unsafe extern "C" fn boot_core1() -> ! {
let mpcore = mpcore::RegisterBlock::mpcore();
mpcore.scu_invalidate.invalidate_core1();
let mmu_table = mmu::L1Table::get()
.setup_flat_layout();
let mmu_table = mmu::L1Table::get();
mmu::with_mmu(mmu_table, || {
ACTLR.enable_smp();
ACTLR.enable_prefetch();
@ -126,6 +128,11 @@ impl Core1 {
}
}
unsafe {
CORE1_ENABLED.set(true);
}
// Flush cache-line
cache::dcc(unsafe { &CORE1_ENABLED });
if sdram {
cache::dccmvac(0);
asm::dsb();