From caa69fda2e3b2c64375ecc978e0f2d73de74bc2e Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Mon, 11 Nov 2019 02:43:05 +0100
Subject: [PATCH] main: refactor into boot

---
 src/boot.rs | 61 +++++++++++++++++++++++++++++++++++++++++++++++++
 src/main.rs | 65 ++---------------------------------------------------
 2 files changed, 63 insertions(+), 63 deletions(-)
 create mode 100644 src/boot.rs

diff --git a/src/boot.rs b/src/boot.rs
new file mode 100644
index 0000000..8312699
--- /dev/null
+++ b/src/boot.rs
@@ -0,0 +1,61 @@
+use r0::zero_bss;
+use crate::regs::{RegisterR, RegisterW};
+use crate::cortex_a9::{asm, regs::*, mmu};
+
+extern "C" {
+    static mut __bss_start: u32;
+    static mut __bss_end: u32;
+    static mut __stack_start: u32;
+}
+
+#[link_section = ".text.boot"]
+#[no_mangle]
+#[naked]
+pub unsafe extern "C" fn _boot_cores() -> ! {
+    const CORE_MASK: u32 = 0x3;
+
+    match MPIDR.read() & CORE_MASK {
+        0 => {
+            SP.write(&mut __stack_start as *mut _ as u32);
+            boot_core0();
+        }
+        _ => loop {
+            // if not core0, infinitely wait for events
+            asm::wfe();
+        },
+    }
+}
+
+#[naked]
+#[inline(never)]
+unsafe fn boot_core0() -> ! {
+    l1_cache_init();
+    zero_bss(&mut __bss_start, &mut __bss_end);
+
+    let mmu_table = mmu::L1Table::get()
+        .setup_flat_layout();
+    mmu::with_mmu(mmu_table, || {
+        crate::main();
+        panic!("return from main");
+    });
+}
+
+fn l1_cache_init() {
+    use crate::cortex_a9::cache::*;
+
+    // Invalidate TLBs
+    tlbiall();
+    // Invalidate I-Cache
+    iciallu();
+    // Invalidate Branch Predictor Array
+    bpiall();
+    // Invalidate D-Cache
+    //
+    // NOTE: It is both faster and correct to only invalidate instead
+    //       of also flush the cache (as was done before with
+    //       `dccisw()`) and it is correct to perform this operation
+    //       for all of the L1 data cache rather than a (previously
+    //       unspecified) combination of one cache set and one cache
+    //       way.
+    dciall();
+}
diff --git a/src/main.rs b/src/main.rs
index 3511841..e2d17d5 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -12,13 +12,13 @@
 extern crate alloc;
 use alloc::{vec, vec::Vec};
 use core::mem::transmute;
-use r0::zero_bss;
 use compiler_builtins as _;
 use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
 use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
 use smoltcp::time::Instant;
 use smoltcp::socket::SocketSet;
 
+mod boot;
 mod regs;
 mod cortex_a9;
 mod abort;
@@ -27,70 +27,9 @@ mod zynq;
 mod stdio;
 mod ram;
 
-use crate::regs::{RegisterR, RegisterW};
-use crate::cortex_a9::{asm, regs::*, mmu};
-
-extern "C" {
-    static mut __bss_start: u32;
-    static mut __bss_end: u32;
-    static mut __stack_start: u32;
-}
-
-#[link_section = ".text.boot"]
-#[no_mangle]
-#[naked]
-pub unsafe extern "C" fn _boot_cores() -> ! {
-    const CORE_MASK: u32 = 0x3;
-
-    match MPIDR.read() & CORE_MASK {
-        0 => {
-            SP.write(&mut __stack_start as *mut _ as u32);
-            boot_core0();
-        }
-        _ => loop {
-            // if not core0, infinitely wait for events
-            asm::wfe();
-        },
-    }
-}
-
-#[naked]
-#[inline(never)]
-unsafe fn boot_core0() -> ! {
-    l1_cache_init();
-    zero_bss(&mut __bss_start, &mut __bss_end);
-
-    let mmu_table = mmu::L1Table::get()
-        .setup_flat_layout();
-    mmu::with_mmu(mmu_table, || {
-        main();
-        panic!("return from main");
-    });
-}
-
-fn l1_cache_init() {
-    use crate::cortex_a9::cache::*;
-
-    // Invalidate TLBs
-    tlbiall();
-    // Invalidate I-Cache
-    iciallu();
-    // Invalidate Branch Predictor Array
-    bpiall();
-    // Invalidate D-Cache
-    //
-    // NOTE: It is both faster and correct to only invalidate instead
-    //       of also flush the cache (as was done before with
-    //       `dccisw()`) and it is correct to perform this operation
-    //       for all of the L1 data cache rather than a (previously
-    //       unspecified) combination of one cache set and one cache
-    //       way.
-    dciall();
-}
-
 const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
 
-fn main() {
+pub fn main() {
     println!("Main.");
 
     let mut ddr = zynq::ddr::DdrRam::new();