From 961e2e1dd0d8bb34fa6f49784f6608b0f2d3f149 Mon Sep 17 00:00:00 2001 From: Astro Date: Sun, 3 Nov 2019 02:22:41 +0100 Subject: [PATCH] zynq::{ddr, eth}: fix clock divisor calculation off-by-one, didn't change behavior. --- src/zynq/ddr/mod.rs | 4 ++-- src/zynq/eth/mod.rs | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index d3b8154..b2c0432 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -56,9 +56,9 @@ impl DdrRam { /// Zynq-7000 AP SoC Technical Reference Manual: /// 10.6.2 DDR IOB Impedance Calibration fn calibrate_iob_impedance(clocks: &CpuClocks) { - let divisor0 = (clocks.ddr / DCI_FREQ) + let divisor0 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ) .max(1).min(63) as u8; - let divisor1 = 1 + (clocks.ddr / DCI_FREQ / u32::from(divisor0)) + let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0)) .max(1).min(63) as u8; let slcr = slcr::RegisterBlock::new(); diff --git a/src/zynq/eth/mod.rs b/src/zynq/eth/mod.rs index 6b7d339..ba6a241 100644 --- a/src/zynq/eth/mod.rs +++ b/src/zynq/eth/mod.rs @@ -192,8 +192,8 @@ impl<'r> Eth<'r, (), ()> { impl<'r, RX, TX> Eth<'r, RX, TX> { pub fn setup_gem0_clock(tx_clock: u32) { let io_pll = CpuClocks::get().io; - let d0 = (io_pll / tx_clock).min(63); - let d1 = (io_pll / tx_clock / d0).min(63); + let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63); + let d1 = (io_pll / tx_clock / d0).max(1).min(63); let slcr = slcr::RegisterBlock::new(); slcr.gem0_clk_ctrl.write( @@ -215,8 +215,8 @@ impl<'r, RX, TX> Eth<'r, RX, TX> { pub fn setup_gem1_clock(tx_clock: u32) { let io_pll = CpuClocks::get().io; - let d0 = (io_pll / tx_clock).min(63); - let d1 = (io_pll / tx_clock / d0).min(63); + let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63); + let d1 = (io_pll / tx_clock / d0).max(1).min(63); let slcr = slcr::RegisterBlock::new(); slcr.gem1_clk_ctrl.write(