srenblad/zynq-rs
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silence static mut ref warns

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This commit is contained in:
Simon Renblad 2025-01-24 17:08:13 +08:00
parent 62c6da3ac5
commit 6871a35dc4
2 changed files with 5 additions and 4 deletions
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3
libcortex_a9/src/mmu.rs
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@ -1,6 +1,7 @@
use bit_field::BitField; use bit_field::BitField;
use super::{regs::*, asm::*, cache::*}; use super::{regs::*, asm::*, cache::*};
use libregister::RegisterW; use libregister::RegisterW;
use core::ptr::{addr_of_mut};
#[derive(Copy, Clone)] #[derive(Copy, Clone)]
#[repr(u8)] #[repr(u8)]
@ -136,7 +137,7 @@ pub struct L1Table {
impl L1Table { impl L1Table {
pub fn get() -> &'static mut Self { pub fn get() -> &'static mut Self {
unsafe { unsafe {
&mut L1_TABLE &mut *addr_of_mut!(L1_TABLE)
} }
} }

6
libsupport_zynq/src/boot.rs
View File

@ -1,5 +1,5 @@
use r0::zero_bss; use r0::zero_bss;
use core::ptr::{addr_of_mut, write_volatile}; use core::ptr::{addr_of, addr_of_mut, write_volatile};
use core::arch::asm; use core::arch::asm;
use libregister::{ use libregister::{
VolatileCell, VolatileCell,
@ -134,7 +134,7 @@ impl Core1 {
CORE1_ENABLED.set(true); CORE1_ENABLED.set(true);
} }
// Flush cache-line // Flush cache-line
cache::dcc(unsafe { &CORE1_ENABLED }); cache::dcc(unsafe { &*addr_of!(CORE1_ENABLED) });
if sdram { if sdram {
cache::dccmvac(0); cache::dccmvac(0);
asm::dsb(); asm::dsb();
@ -155,7 +155,7 @@ impl Core1 {
pub fn disable(&self) { pub fn disable(&self) {
unsafe { unsafe {
CORE1_ENABLED.set(false); CORE1_ENABLED.set(false);
cache::dccmvac(&CORE1_ENABLED as *const _ as usize); cache::dccmvac(addr_of!(CORE1_ENABLED) as usize);
asm::dsb(); asm::dsb();
} }
self.restart(); self.restart();