From 6871a35dc4b7323ee4f7450f40e7270d98e5603c Mon Sep 17 00:00:00 2001
From: Simon Renblad <srenblad@m-labs.hk>
Date: Fri, 24 Jan 2025 17:08:13 +0800
Subject: [PATCH] silence static mut ref warns

---
 libcortex_a9/src/mmu.rs     | 3 ++-
 libsupport_zynq/src/boot.rs | 6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/libcortex_a9/src/mmu.rs b/libcortex_a9/src/mmu.rs
index 4c72e48..14b5c5b 100644
--- a/libcortex_a9/src/mmu.rs
+++ b/libcortex_a9/src/mmu.rs
@@ -1,6 +1,7 @@
 use bit_field::BitField;
 use super::{regs::*, asm::*, cache::*};
 use libregister::RegisterW;
+use core::ptr::{addr_of_mut};
 
 #[derive(Copy, Clone)]
 #[repr(u8)]
@@ -136,7 +137,7 @@ pub struct L1Table {
 impl L1Table {
     pub fn get() -> &'static mut Self {
         unsafe {
-            &mut L1_TABLE
+            &mut *addr_of_mut!(L1_TABLE)
         }
     }
 
diff --git a/libsupport_zynq/src/boot.rs b/libsupport_zynq/src/boot.rs
index 66bc70a..ba4a0c1 100644
--- a/libsupport_zynq/src/boot.rs
+++ b/libsupport_zynq/src/boot.rs
@@ -1,5 +1,5 @@
 use r0::zero_bss;
-use core::ptr::{addr_of_mut, write_volatile};
+use core::ptr::{addr_of, addr_of_mut, write_volatile};
 use core::arch::asm;
 use libregister::{
     VolatileCell,
@@ -134,7 +134,7 @@ impl Core1 {
             CORE1_ENABLED.set(true);
         }
         // Flush cache-line
-        cache::dcc(unsafe { &CORE1_ENABLED });
+        cache::dcc(unsafe { &*addr_of!(CORE1_ENABLED) });
         if sdram {
             cache::dccmvac(0);
             asm::dsb();
@@ -155,7 +155,7 @@ impl Core1 {
     pub fn disable(&self) {
         unsafe {
             CORE1_ENABLED.set(false);
-            cache::dccmvac(&CORE1_ENABLED  as *const _ as usize);
+            cache::dccmvac(addr_of!(CORE1_ENABLED) as usize);
             asm::dsb();
         }
         self.restart();