diff --git a/experiments/src/main.rs b/experiments/src/main.rs
index d5d0cbd..4d17ba1 100644
--- a/experiments/src/main.rs
+++ b/experiments/src/main.rs
@@ -42,6 +42,7 @@ use libsupport_zynq::{
 };
 use log::{info, warn};
 use core::sync::atomic::{AtomicBool, Ordering};
+use core::ptr::addr_of_mut;
 
 const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
 
diff --git a/libcortex_a9/src/lib.rs b/libcortex_a9/src/lib.rs
index b124a38..258dc26 100644
--- a/libcortex_a9/src/lib.rs
+++ b/libcortex_a9/src/lib.rs
@@ -1,5 +1,6 @@
 #![no_std]
 #![feature(never_type)]
+#![feature(ptr_as_ref_unchecked)]
 
 extern crate alloc;
 
diff --git a/libcortex_a9/src/mmu.rs b/libcortex_a9/src/mmu.rs
index 4c72e48..3fa1668 100644
--- a/libcortex_a9/src/mmu.rs
+++ b/libcortex_a9/src/mmu.rs
@@ -1,4 +1,5 @@
 use bit_field::BitField;
+use core::ptr::{addr_of_mut, addr_of};
 use super::{regs::*, asm::*, cache::*};
 use libregister::RegisterW;
 
@@ -134,9 +135,9 @@ pub struct L1Table {
 }
 
 impl L1Table {
-    pub fn get() -> &'static mut Self {
+    pub fn get() -> *mut L1Table {
         unsafe {
-            &mut L1_TABLE
+            addr_of_mut!(L1_TABLE)
         }
     }
 
@@ -391,7 +392,7 @@ pub fn with_mmu<F: FnMut() -> !>(l1table: &L1Table, mut f: F) -> ! {
     let domains = AccessDomains::all_manager();
     DACR.write(domains.into());
 
-    let table_base = &l1table.table as *const _ as u32;
+    let table_base = addr_of!(l1table.table) as u32;
     assert!(table_base & 0x3fff == 0);
     TTBR0.write(
         TTBR0::zeroed()
diff --git a/libcortex_a9/src/uncached.rs b/libcortex_a9/src/uncached.rs
index fc016b2..dd1dbe1 100644
--- a/libcortex_a9/src/uncached.rs
+++ b/libcortex_a9/src/uncached.rs
@@ -23,13 +23,16 @@ impl<T> UncachedSlice<T> {
         assert_eq!(start & (L1_PAGE_SIZE - 1), 0);
 
         for page_start in (start..(start + size)).step_by(L1_PAGE_SIZE) {
-            // non-shareable device
-            L1Table::get()
-                .update(page_start as *const (), |l1_section| {
-                    l1_section.tex = 0b10;
-                    l1_section.cacheable = true;
-                    l1_section.bufferable = false;
-                });
+            unsafe {
+                // non-shareable device
+                L1Table::get()
+                    .as_mut_unchecked()
+                    .update(page_start as *const (), |l1_section| {
+                        l1_section.tex = 0b10;
+                        l1_section.cacheable = true;
+                        l1_section.bufferable = false;
+                    });
+            }
         }
 
         let slice = unsafe { core::slice::from_raw_parts_mut(ptr, len) };
diff --git a/libsupport_zynq/src/boot.rs b/libsupport_zynq/src/boot.rs
index 9b32b9d..89edcde 100644
--- a/libsupport_zynq/src/boot.rs
+++ b/libsupport_zynq/src/boot.rs
@@ -1,5 +1,5 @@
 use r0::zero_bss;
-use core::ptr::{addr_of_mut, write_volatile};
+use core::ptr::{write_volatile, addr_of_mut};
 use core::arch::asm;
 use libregister::{
     VolatileCell,
@@ -45,8 +45,11 @@ unsafe extern "C" fn boot_core0() -> ! {
 
     zero_bss(addr_of_mut!(__bss_start), addr_of_mut!(__bss_end));
 
-    let mmu_table = mmu::L1Table::get()
-        .setup_flat_layout();
+    let mmu_table = unsafe { 
+        mmu::L1Table::get()
+            .as_mut().unwrap()
+            .setup_flat_layout()
+    };
     mmu::with_mmu(mmu_table, || {
         mpcore.scu_control.start();
         ACTLR.enable_smp();
@@ -69,8 +72,11 @@ unsafe extern "C" fn boot_core1() -> ! {
     let mpcore = mpcore::RegisterBlock::mpcore();
     mpcore.scu_invalidate.invalidate_core1();
 
-    let mmu_table = mmu::L1Table::get()
-        .setup_flat_layout();
+    let mmu_table = unsafe {
+        mmu::L1Table::get()
+            .as_mut().unwrap()
+            .setup_flat_layout()
+    };
     mmu::with_mmu(mmu_table, || {
         ACTLR.enable_smp();
         ACTLR.enable_prefetch();