forked from sinara-hw/assembly
Add clocker, grabber (draft), almazny, sampler, fastino, master-satellite instructions
Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
parent
8888364cb8
commit
bc20eb0de7
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@ -28,7 +28,9 @@ Tips for adding hardware instructions:
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1. Compose a chapter in a new Markdown file in `src/hw`
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1. Compose a chapter in a new Markdown file in `src/hw`
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2. Add pictures if needed, store them in `src/img`, assure them to be clear, informative and compressed
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2. Add pictures if needed, store them in `src/img`, assure them to be clear, informative and compressed
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(you can use `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> <OUTPUT IMAGE>` for optimizing)
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(you can use `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> <OUTPUT IMAGE>` for optimizing JPEG image
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or `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> -background white -alpha remove -alpha off <OUTPUT IMAGE>`
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for images with transparent background)
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3. Add link to the new chapter to the `src/SUMMARY.md`
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3. Add link to the new chapter to the `src/SUMMARY.md`
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4. Do not forget to tell about all hidden/non-obvious obstacles and pitfalls
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4. Do not forget to tell about all hidden/non-obvious obstacles and pitfalls
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5. Add testing steps, even the "obvious" ones
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5. Add testing steps, even the "obvious" ones
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@ -3,9 +3,12 @@
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- [Build and test firmware](./build_test_firmware.md)
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- [Build and test firmware](./build_test_firmware.md)
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- [Hardware](./hw/hardware.md)
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- [Hardware](./hw/hardware.md)
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- [Sinara 4624 AWG Phaser (Upconverter)](./hw/phaser_upconverter.md)
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- [Sinara 4624 AWG Phaser (Upconverter)](./hw/phaser_upconverter.md)
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- [Sinara 4456 synthesizer Mirny](./hw/mirny.md)
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- [Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card](./hw/mirny_almazny.md)
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- [SUServo (Sampler + Urukul)](./hw/suservo.md)
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- [SUServo (Sampler + Urukul)](./hw/suservo.md)
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- [Sinara 2118 BNC-TTL / 2128 SMA-TTL](./hw/bnc_sma_ttl.md)
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- [Sinara 2118 BNC-TTL / 2128 SMA-TTL](./hw/bnc_sma_ttl.md)
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- [Sinara 5432 DAC Zotino](./hw/zotino.md)
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- [Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino](./hw/zotino_fastino.md)
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- [Sinara 5518 BNC-IDC / 5528 SMA-IDC adapter](./hw/bnc_sma_idc_adapter.md)
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- [Sinara 5518 BNC-IDC / 5528 SMA-IDC adapter](./hw/bnc_sma_idc_adapter.md)
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- [Sinara 4410/4412 DDS "Urukul" (AD9910/AD9912)](./hw/urukul.md)
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- [Sinara 4410/4412 DDS Urukul (AD9910/AD9912)](./hw/urukul.md)
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- [Sinara 5108 Sampler](./hw/sampler.md)
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- [Sinara 6302 Grabber](./hw/grabber.md)
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- [Sinara 7210 Clocker](./hw/clocker.md)
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@ -27,4 +27,45 @@ artiq_sinara_tester
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```
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```
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Follow `artiq_sinara_tester` instructions for testing the hardware. For more detailed information,
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Follow `artiq_sinara_tester` instructions for testing the hardware. For more detailed information,
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you can use this book's pages, or if there is no instruction for testing your hardware, please add them to this book.
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you can use this book's pages, or if there is no instruction for testing your hardware, please add them to this book.
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## Kasli-SoC (zynq)
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### Checklist
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1. Build firmware (see commands below) for SD card variant
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2. Copy `results/boot.bin` to the SD card
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3. Insert SD card to the Kasli-SoC and boot
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4. Change IP from the default one: `artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75`
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5. Reboot and check it works on new IP address
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6. Test hardware
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7. Create a flash-drive with `device_db.py` file for customers (FAT32)
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### CLI commands
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```shell
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mkdir <variant>
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cd <variant>/
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git clone gitea@git.m-labs.hk:M-Labs/artiq-zynq.git
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cd artiq-zynq/
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git checkout origin/release-7
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nix develop
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artiq_ddb_template -o device_db.py <variant>.json
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nix build -L --impure --expr 'let fl = builtins.getFlake "git+file://<path to artiq_zynq repo>"; in (fl.makeArtiqZynqPackage {target="kasli_soc"; variant="[master, standalone, satellite]"; json=<path to the json description>;}).kasli_soc-[master, standalone, satellite]-sd'
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# copy `results/boot.bin` to the SD card
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# insert SD card to the Kasli-SoC and boot
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artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75
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# reboot via power supply
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artiq_sinara_tester
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```
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## Master-satellite setups
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1. Change `base` in JSON to the respective `master` or `satellite`, add `"enable_sata_drtio": true` if needed to the master,
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remove `core_addr` in satellites
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2. Build and flash firmware for each crate with JSONs (see instructions above)
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3. Create composed `device_db.py`: `artiq_ddb_template -o device_db.py -s 1 <satellite1>.json -s 2 <satellite2>.json <master>.json`
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4. Connect satellite crates to the master respective to their numbers via the fiber (see example picture)
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![](img/master_sat_connection.jpg)
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5. Ethernet is needed only for master
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6. Test hardware as it would be one crate
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@ -3,11 +3,11 @@
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## JSON
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## JSON
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There is no JSON description for this hardware, as it is an adapter,
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There is no JSON description for this hardware, as it is an adapter,
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connected to the Zotino and not the Kasli. See [Zotino page](./zotino.md).
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connected to the Zotino/Fastino and not the Kasli. See [Zotino/Fastino page](./zotino_fastino.md).
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## Setup
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## Setup
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BNC/SMA-IDC adapters should be connected to the Zotino with 26 pin cable only. Be aware of the order of the Zotino's ports -
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BNC/SMA-IDC adapters should be connected to the Zotino/Fastino with 26 pin cable only. Be aware of the order of the Zotino/Fastino's ports -
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see numbers of the channels at the board when connecting.
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see numbers of the channels at the board when connecting.
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## Testing
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## Testing
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@ -15,12 +15,12 @@ see numbers of the channels at the board when connecting.
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After running `artiq_sinara_test`:
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After running `artiq_sinara_test`:
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```text
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```text
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*** Testing Zotino DACs and USER LEDs.
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*** Testing Zotino/Fastino DACs and USER LEDs.
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Voltages:
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Voltages:
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zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
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zotino0/fastino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
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Press ENTER when done.
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Press ENTER when done.
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```
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```
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Similar to Zotino, check output voltages on the BNC/SMA connectors with multimeter, alongside on the Zotino itself.
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Similar to Zotino/Fastino, check output voltages on the BNC/SMA connectors with multimeter, alongside on the Zotino/Fastino itself.
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These voltages should be very close to the respective `artiq_sinara_test`'s suggested voltages.
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These voltages should be very close to the respective `artiq_sinara_test`'s suggested voltages.
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See [Zotino page](./zotino.md) for details.
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See [Zotino/Fastino page](./zotino_fastino.md) for details.
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@ -0,0 +1,52 @@
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# Sinara 7210 Clocker
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[Wiki](https://github.com/sinara-hw/Clocker/wiki)
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## JSON
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Put the `ext_ref_frequency` field into the JSON description if the Clocker is going to use an external frequency:
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```json
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{
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"hw_rev": "<hw rev>",
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"base": "<base>",
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...
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"ext_ref_frequency": <freq in Hz>,
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...
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"peripherals": [...]
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}
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```
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On peripherals you should choose `"clk_sel": 2` on connected devices.
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## Setup
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For tests, you may need an external RF generator, depending on customer needs.
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Here is example setup for SynthNV RF signal generator:
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1. Connect SynthNV to the workstation via USB, and
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2. Install and run `cutecom`: `nix-shell -p cutecom`
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3. Set settings as on the picture below:
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![](../img/cutecom_settings.png)
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4. Open the device, usually it is `/dev/ttyACM0`
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5. Put `?` into `Input` field and press `Enter` for current settings and help commands
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6. For changing the frequency, enter `f<freq in MHz>`, e.g. `f125.0` for 125 MHz
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7. Set RF power so that clocker would recognize the signal with `a<power>` command, e.g. `a63`
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8. Check for desired amplitude and frequency at the `RFOut` (see picture below for reference) pin via oscilloscope
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![](../img/synthnv_pins.jpg)
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9. If everything is ok, connect `RFOut` to the `CLK IN` on the Clocker (see instructions below for details)
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### Setup the Clocker
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1. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference)
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2. Connect the Clocker to the Kasli via 30-pin ports
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![](../img/clocker_ref.jpg)
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3. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin
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4. After assembling the crates and flashing the firmware, start Kasli and write config as follows:
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`artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
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for the details and available options
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5. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command
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## Testing
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Run `artiq_sinara_test` and check that it doesn't fail on the connected devices.
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@ -0,0 +1,20 @@
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# Sinara 6302 Grabber
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## JSON
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```json
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{
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"type": "grabber",
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"ports": [<port num>, <optional port num>, <optional port num>]
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}
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```
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## Testing
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```text
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*** Testing Grabber Frame Grabbers.
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Activate the camera's frame grabber output, type 'g', press ENTER, and trigger the camera.
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Just press ENTER to skip the test.
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```
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**TODO**
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@ -1,44 +0,0 @@
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# Sinara 4456 synthesizer Mirny
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[Wiki](https://github.com/sinara-hw/mirny/wiki)
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## JSON
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```json
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{
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"type": "mirny",
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"ports": [<port num>]
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}
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```
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## Testing
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```text
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*** Testing Mirny PLLs.
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Initializing CPLDs...
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mirny0_cpld...
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...done
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All mirny channels active.
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Frequencies:
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mirny0_ch0 1000MHz
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mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch1 1100MHz
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mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch2 1200MHz
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mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch3 1300MHz
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mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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```
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After running `artiq_sinara_test`:
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1. Install gqrx `nix-shell -p gqrx`
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2. Connect bladeRF via USB cable only
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3. Run gqrx and choose `BladeRF #<number>...`
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4. Default settings
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5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
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6. Connect the probe through attenuator to the Mirny's port
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7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
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8. Repeat 5-7 for every channel
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![](../img/mirny_gqrx.png)
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@ -0,0 +1,98 @@
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# Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card
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[Wiki Mirny](https://github.com/sinara-hw/mirny/wiki)
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[Wiki Almazny](https://github.com/sinara-hw/Almazny/wiki)
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## JSON
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```json
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{
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"type": "mirny",
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"almazny": true, // for mirny with almazny only
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"ports": [<port num>]
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}
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```
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## Testing
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### Without Almazny
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```text
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*** Testing Mirny PLLs.
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Initializing CPLDs...
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mirny0_cpld...
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...done
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All mirny channels active.
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Frequencies:
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mirny0_ch0 1000MHz
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mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch1 1100MHz
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mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch2 1200MHz
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mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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mirny0_ch3 1300MHz
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mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
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```
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After running `artiq_sinara_test`:
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1. Install gqrx `nix-shell -p gqrx`
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2. Connect bladeRF via USB cable only
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3. Run gqrx and choose `BladeRF #<number>...`
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4. Default settings
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5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
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6. Connect the probe through attenuator to the Mirny's port
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7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
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8. Repeat 5-7 for every channel
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![](../img/mirny_gqrx.png)
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### With Almazny
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At first, `artiq_sinara_test` will prompt you for testing Mirnies as the would be without Almazny.
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After that, it will prompt you with testing the Almazny:
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```text
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*** Testing Almaznys.
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||||||
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mirny1_almazny...
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Initializing Mirny CPLDs...
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mirny0_cpld...
|
||||||
|
mirny1_cpld...
|
||||||
|
...done
|
||||||
|
Testing attenuators. Frequencies:
|
||||||
|
mirny0_ch0 4000MHz
|
||||||
|
mirny0_ch0 info: {'f_outA': 2000000000.0, 'f_outB': 8000000000, 'output_divider': 2, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny0_ch1 4100MHz
|
||||||
|
mirny0_ch1 info: {'f_outA': 2050000000.0, 'f_outB': 8200000000, 'output_divider': 2, 'f_vco': 4100000000, 'pll_n': 41, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny0_ch2 4200MHz
|
||||||
|
mirny0_ch2 info: {'f_outA': 2100000000.0, 'f_outB': 8400000000, 'output_divider': 2, 'f_vco': 4200000000, 'pll_n': 42, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny0_ch3 4300MHz
|
||||||
|
mirny0_ch3 info: {'f_outA': 2150000000.0, 'f_outB': 8600000000, 'output_divider': 2, 'f_vco': 4300000000, 'pll_n': 43, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny1_ch0 4500MHz
|
||||||
|
mirny1_ch0 info: {'f_outA': 2250000000.0, 'f_outB': 9000000000, 'output_divider': 2, 'f_vco': 4500000000, 'pll_n': 45, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny1_ch1 4600MHz
|
||||||
|
mirny1_ch1 info: {'f_outA': 2300000000.0, 'f_outB': 9200000000, 'output_divider': 2, 'f_vco': 4600000000, 'pll_n': 46, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny1_ch2 4700MHz
|
||||||
|
mirny1_ch2 info: {'f_outA': 2350000000.0, 'f_outB': 9400000000, 'output_divider': 2, 'f_vco': 4700000000, 'pll_n': 47, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
mirny1_ch3 4800MHz
|
||||||
|
mirny1_ch3 info: {'f_outA': 2400000000.0, 'f_outB': 9600000000, 'output_divider': 2, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
|
||||||
|
RF ON, all attenuators ON. Press ENTER when done.
|
||||||
|
|
||||||
|
RF ON, half power attenuators ON. Press ENTER when done.
|
||||||
|
|
||||||
|
RF ON, all attenuators OFF. Press ENTER when done.
|
||||||
|
|
||||||
|
SR outputs are OFF. Press ENTER when done.
|
||||||
|
|
||||||
|
RF ON, all attenuators are ON. Press ENTER when done.
|
||||||
|
|
||||||
|
RF OFF. Press ENTER when done.
|
||||||
|
```
|
||||||
|
|
||||||
|
Similar to _Without Almazny_, check mirnies' channels emissions on defined frequencies.
|
||||||
|
You should also see differences in various modes, but that may require disabling the gain.
|
||||||
|
|
||||||
|
|
||||||
|
### Tips
|
||||||
|
|
||||||
|
Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).
|
|
@ -0,0 +1,35 @@
|
||||||
|
# Sinara 5108 Sampler
|
||||||
|
|
||||||
|
## JSON
|
||||||
|
|
||||||
|
```json
|
||||||
|
{
|
||||||
|
"type": "sampler",
|
||||||
|
"ports": [<port num>, <port num>],
|
||||||
|
"hw_rev": "<hw rev>" // optional
|
||||||
|
}
|
||||||
|
```
|
||||||
|
|
||||||
|
## Testing
|
||||||
|
|
||||||
|
After running `artiq_sinara_test`:
|
||||||
|
|
||||||
|
```text
|
||||||
|
*** Testing Sampler ADCs.
|
||||||
|
Testing: samplerX
|
||||||
|
Apply 1.5V to channel 0. Press ENTER when done.
|
||||||
|
|
||||||
|
PASSED
|
||||||
|
Apply 1.5V to channel 1. Press ENTER when done.
|
||||||
|
|
||||||
|
...
|
||||||
|
|
||||||
|
PASSED
|
||||||
|
Apply 1.5V to channel 7. Press ENTER when done.
|
||||||
|
|
||||||
|
PASSED
|
||||||
|
```
|
||||||
|
|
||||||
|
1. Apply 1.5V (connect the AA-battery) to the `samplerX`'s requested channel
|
||||||
|
2. Press `Enter`, the `artiq_sinara_test` should output `PASSED`
|
||||||
|
3. Repeat steps 1-2 for every available channel.
|
|
@ -6,8 +6,8 @@
|
||||||
{
|
{
|
||||||
"type": "suservo",
|
"type": "suservo",
|
||||||
"sampler_ports": [<port num>, <port num>],
|
"sampler_ports": [<port num>, <port num>],
|
||||||
"urukulN_ports": [<port num>, <port num>],
|
"urukul0_ports": [<port num>, <port num>],
|
||||||
"urukulM_ports": [<port num>, <port num>], // optional
|
"urukul1_ports": [<port num>, <port num>], // optional
|
||||||
"clk_sel": 2
|
"clk_sel": 2
|
||||||
}
|
}
|
||||||
```
|
```
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
# Sinara 4410/4412 DDS "Urukul" (AD9910/AD9912)
|
# Sinara 4410/4412 DDS Urukul (AD9910/AD9912)
|
||||||
|
|
||||||
* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/4410-4412.pdf)
|
* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/4410-4412.pdf)
|
||||||
* [Wiki](https://github.com/sinara-hw/Urukul/wiki)
|
* [Wiki](https://github.com/sinara-hw/Urukul/wiki)
|
||||||
|
|
|
@ -1,29 +0,0 @@
|
||||||
# Sinara 5432 DAC Zotino
|
|
||||||
|
|
||||||
* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/5432.pdf)
|
|
||||||
* [Wiki](https://github.com/sinara-hw/Zotino/wiki)
|
|
||||||
|
|
||||||
## JSON
|
|
||||||
|
|
||||||
```json
|
|
||||||
{
|
|
||||||
"type": "zotino",
|
|
||||||
"ports": [<port num>]
|
|
||||||
}
|
|
||||||
```
|
|
||||||
|
|
||||||
## Testing
|
|
||||||
|
|
||||||
After running `artiq_sinara_test`:
|
|
||||||
|
|
||||||
```text
|
|
||||||
*** Testing Zotino DACs and USER LEDs.
|
|
||||||
Voltages:
|
|
||||||
zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
|
|
||||||
Press ENTER when done.
|
|
||||||
```
|
|
||||||
|
|
||||||
1. Touch with multimeter/DC voltmeter each pair of pins from bottom to top (left pins are ground)
|
|
||||||
2. Check that respective pins have voltages as described by `artiq_sinara_test`
|
|
||||||
3. If there are [BNC/SMA-IDC adapters](./bnc_sma_idc_adapter.md), also check their voltages - they should be the same
|
|
||||||
4. Check LEDs are on
|
|
|
@ -0,0 +1,47 @@
|
||||||
|
# Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino
|
||||||
|
|
||||||
|
* [Datasheet Zotino](https://m-labs.hk/docs/sinara-datasheets/5432.pdf)
|
||||||
|
* [Wiki Zotino](https://github.com/sinara-hw/Zotino/wiki)
|
||||||
|
* [Wiki Fastino](https://github.com/sinara-hw/Fastino/wiki)
|
||||||
|
|
||||||
|
## JSON
|
||||||
|
|
||||||
|
```json
|
||||||
|
{
|
||||||
|
"type": "zotino",
|
||||||
|
"ports": [<port num>]
|
||||||
|
}
|
||||||
|
```
|
||||||
|
```json
|
||||||
|
{
|
||||||
|
"type": "fastino",
|
||||||
|
"hw_rev": "v1.2", // optional
|
||||||
|
"ports": [<port num>]
|
||||||
|
}
|
||||||
|
```
|
||||||
|
|
||||||
|
## Setup
|
||||||
|
|
||||||
|
Connect the BNC/SMA-IDC adapters to the Zotino/Fastino with 26-pin cable if needed by customer. Be aware of the ports order -
|
||||||
|
see reference numbers on the board.
|
||||||
|
|
||||||
|
## Testing
|
||||||
|
|
||||||
|
After running `artiq_sinara_test`:
|
||||||
|
|
||||||
|
```text
|
||||||
|
*** Testing Zotino DACs and USER LEDs.
|
||||||
|
Voltages:
|
||||||
|
zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
|
||||||
|
Press ENTER when done.
|
||||||
|
|
||||||
|
*** Testing Fastino DACs and USER LEDs.
|
||||||
|
Voltages:
|
||||||
|
fastino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
|
||||||
|
Press ENTER when done.
|
||||||
|
```
|
||||||
|
|
||||||
|
1. Touch with multimeter/DC voltmeter each pair of pins from bottom to top (left pins are ground)
|
||||||
|
2. Check that respective pins have voltages as described by `artiq_sinara_test`
|
||||||
|
3. If there are [BNC/SMA-IDC adapters](./bnc_sma_idc_adapter.md), also check their voltages - they should be the same
|
||||||
|
4. Check LEDs are on
|
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Loading…
Reference in New Issue