forked from sinara-hw/assembly
urukul: add note on clk_div with pll disabled
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@ -149,3 +149,24 @@ ValueError: Urukul AD9910 AUX_DAC mismatch
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```
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```
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Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
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Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
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### Jagged signal with 1GHz external clock on AD9910
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By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.
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Change the ``clk_div`` parameter to the CPLD in the device_db file:
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```python
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device_db["urukulX_cpld"] = {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"sync_device": None,
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 1000000000.0,
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"clk_sel": 1,
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"clk_div" : 1 # <--- add this line
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}
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}
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```
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