From 097f4e8cec62667d6727666e3f565c3f1fdde316 Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Thu, 13 Jul 2023 11:59:33 +0800 Subject: [PATCH] Add synchronisation description to urukul (#4) Signed-off-by: Egor Savkin --- src/hw/urukul.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/hw/urukul.md b/src/hw/urukul.md index c77ed4b..897e8bd 100644 --- a/src/hw/urukul.md +++ b/src/hw/urukul.md @@ -12,6 +12,7 @@ "dds": "", // ad9910/ad9912 "ports": [, ], // second port is optional "clk_sel": , + "synchronization": true/false, // for AD9910 only "refclk": , // for external clock signal "pll_en": <0 or 1, default 1> // PLL bypass, to allow higher external clocker frequencies (1e9 for example) } @@ -21,6 +22,16 @@ Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source. +### Synchronization + +Synchronization option in the JSON refers to the phase synchronization between the outputs, and can be used only on AD9910 variants and +only with 125 MHz clock source provided from Kasli/Kasli-SoC (may be relayed through the Clocker board). +The phase sync works only within one Urukul board, though the phase shift between Urukuls may be [predictable](https://github.com/m-labs/artiq/issues/1692#issuecomment-994439589). +Even though it is widely-desirable feature, there are drawbacks of this preventing from enabling by default: +1. The resulting signal is more noisy, which can be observed [previously](https://github.com/sinara-hw/Urukul/issues/64). +2. Phase sync process takes time and sometimes fails +3. ??? + ## Testing After running `artiq_sinara_test`: