forked from M-Labs/artiq
26 lines
865 B
Python
26 lines
865 B
Python
from artiq.language.experiment import *
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from artiq.language.units import *
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class DDS:
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def __init__(self, core, reg_channel, rtio_channel, latency=0*ps, phase_mode="continuous"):
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self.core = core
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self.reg_channel = reg_channel
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self.rtio_channel = rtio_channel
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self.latency = latency
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self.phase_mode = phase_mode
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self._previous_frequency = 0*MHz
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kernel_attr_ro = "reg_channel rtio_channel latency phase_mode"
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kernel_attr = "_previous_frequency"
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@kernel
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def pulse(self, frequency, duration):
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if self._previous_frequency != frequency:
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syscall("rtio_sync", self.rtio_channel) # wait until output is off
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syscall("dds_program", self.reg_channel, frequency)
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self._previous_frequency = frequency
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syscall("rtio_set", now()-self.latency, self.rtio_channel, 1)
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delay(duration)
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syscall("rtio_set", now()-self.latency, self.rtio_channel, 0)
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