forked from M-Labs/artiq
394 lines
15 KiB
Python
394 lines
15 KiB
Python
from artiq.language.core import *
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from artiq.language.types import *
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from artiq.language.units import *
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from artiq.coredevice.rtio import rtio_output
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from artiq.coredevice.exceptions import DDSError
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from numpy import int32, int64
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_PHASE_MODE_DEFAULT = -1
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PHASE_MODE_CONTINUOUS = 0
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PHASE_MODE_ABSOLUTE = 1
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PHASE_MODE_TRACKING = 2
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class DDSParams:
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def __init__(self):
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self.bus_channel = 0
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self.channel = 0
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self.ftw = 0
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self.pow = 0
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self.phase_mode = 0
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self.amplitude = 0
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class BatchContextManager:
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kernel_invariants = {"core", "core_dds", "params"}
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def __init__(self, core_dds):
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self.core_dds = core_dds
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self.core = self.core_dds.core
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self.active = False
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self.params = [DDSParams() for _ in range(16)]
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self.count = 0
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self.ref_time = int64(0)
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@kernel
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def __enter__(self):
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"""Starts a DDS command batch. All DDS commands are buffered
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after this call, until ``batch_exit`` is called.
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The time of execution of the DDS commands is the time cursor position
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when the batch is entered."""
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if self.active:
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raise DDSError("DDS batch entered twice")
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self.active = True
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self.count = 0
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self.ref_time = now_mu()
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@kernel
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def append(self, bus_channel, channel, ftw, pow, phase_mode, amplitude):
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if self.count == len(self.params):
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raise DDSError("Too many commands in DDS batch")
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params = self.params[self.count]
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params.bus_channel = bus_channel
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params.channel = channel
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params.ftw = ftw
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params.pow = pow
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params.phase_mode = phase_mode
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params.amplitude = amplitude
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self.count += 1
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@kernel
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def __exit__(self, type, value, traceback):
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"""Ends a DDS command batch. All buffered DDS commands are issued
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on the bus."""
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if not self.active:
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raise DDSError("DDS batch exited twice")
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self.active = False
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at_mu(self.ref_time - self.core_dds.batch_duration_mu())
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for i in range(self.count):
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param = self.params[i]
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self.core_dds.program(self.ref_time,
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param.bus_channel, param.channel, param.ftw,
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param.pow, param.phase_mode, param.amplitude)
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class DDSGroup:
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"""Core device Direct Digital Synthesis (DDS) driver.
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Gives access to the DDS functionality of the core device.
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:param sysclk: DDS system frequency. The DDS system clock must be a
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phase-locked multiple of the RTIO clock.
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"""
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kernel_invariants = {"core", "sysclk", "batch"}
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def __init__(self, dmgr, sysclk, core_device="core"):
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self.core = dmgr.get(core_device)
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self.sysclk = sysclk
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self.batch = BatchContextManager(self)
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@kernel
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def batch_duration_mu(self):
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raise NotImplementedError
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@kernel
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def init(self, bus_channel, channel):
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raise NotImplementedError
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@kernel
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def program(self, ref_time, bus_channel, channel, ftw, pow, phase_mode, amplitude):
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raise NotImplementedError
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@kernel
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def set(self, bus_channel, channel, ftw, pow, phase_mode, amplitude):
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if self.batch.active:
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self.batch.append(bus_channel, channel, ftw, pow, phase_mode, amplitude)
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else:
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ref_time = now_mu()
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at_mu(ref_time - self.program_duration_mu)
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self.program(ref_time,
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bus_channel, channel, ftw, pow, phase_mode, amplitude)
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(float(int64(2)**32*frequency/self.sysclk))
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@portable(flags={"fast-math"})
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw*self.sysclk/int64(2)**32
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@portable(flags={"fast-math"})
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def turns_to_pow(self, turns):
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"""Returns the phase offset word corresponding to the given phase
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in turns."""
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return round(float(turns*2**self.pow_width))
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@portable(flags={"fast-math"})
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def pow_to_turns(self, pow):
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"""Returns the phase in turns corresponding to the given phase offset
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word."""
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return pow/2**self.pow_width
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@portable(flags={"fast-math"})
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def amplitude_to_asf(self, amplitude):
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"""Returns amplitude scale factor corresponding to given amplitude."""
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return round(float(amplitude*0x0fff))
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@portable(flags={"fast-math"})
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def asf_to_amplitude(self, asf):
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"""Returns the amplitude corresponding to the given amplitude scale
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factor."""
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return asf/0x0fff
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class DDSChannel:
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"""Core device Direct Digital Synthesis (DDS) channel driver.
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Controls one DDS channel managed directly by the core device's runtime.
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This class should not be used directly, instead, use the chip-specific
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drivers such as ``DDSChannelAD9914``.
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The time cursor is not modified by any function in this class.
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:param bus: name of the DDS bus device that this DDS is connected to.
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:param channel: channel number of the DDS device to control.
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"""
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kernel_invariants = {
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"core", "core_dds", "bus_channel", "channel",
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}
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def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):
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self.core_dds = dmgr.get(core_dds_device)
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self.core = self.core_dds.core
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self.bus_channel = bus_channel
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self.channel = channel
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@kernel
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def init(self):
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"""Resets and initializes the DDS channel.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 2ms provides a good
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timing margin."""
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self.core_dds.init(self.bus_channel, self.channel)
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@kernel
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def set_phase_mode(self, phase_mode):
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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* ``PHASE_MODE_CONTINUOUS``: the phase accumulator is unchanged when
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switching frequencies. The DDS phase is the sum of the phase
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accumulator and the phase offset. The only discrete jumps in the
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DDS output phase come from changes to the phase offset.
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* ``PHASE_MODE_ABSOLUTE``: the phase accumulator is reset when
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switching frequencies. Thus, the phase of the DDS at the time of
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the frequency change is equal to the phase offset.
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* ``PHASE_MODE_TRACKING``: when switching frequencies, the phase
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accumulator is set to the value it would have if the DDS had been
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running at the specified frequency since the start of the
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experiment.
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"""
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self.phase_mode = phase_mode
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@kernel
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def set_mu(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT,
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amplitude=0x0fff):
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"""Sets the DDS channel to the specified frequency and phase.
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This uses machine units (FTW and POW). The frequency tuning word width
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is 32, whereas the phase offset word width depends on the type of DDS
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chip and can be retrieved via the ``pow_width`` attribute. The amplitude
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width is 12.
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The "frequency update" pulse is sent to the DDS with a fixed latency
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with respect to the current position of the time cursor.
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:param frequency: frequency to generate.
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:param phase: adds an offset, in turns, to the phase.
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:param phase_mode: if specified, overrides the default phase mode set
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by ``set_phase_mode`` for this call.
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"""
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if phase_mode == _PHASE_MODE_DEFAULT:
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phase_mode = self.phase_mode
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self.core_dds.set(self.bus_channel, self.channel, frequency, phase, phase_mode, amplitude)
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@kernel
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def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT,
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amplitude=1.0):
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"""Like ``set_mu``, but uses Hz and turns."""
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self.set_mu(self.core_dds.frequency_to_ftw(frequency),
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self.core_dds.turns_to_pow(phase), phase_mode,
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self.core_dds.amplitude_to_asf(amplitude))
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AD9914_REG_CFR1L = 0x01
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AD9914_REG_CFR1H = 0x03
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AD9914_REG_CFR2L = 0x05
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AD9914_REG_CFR2H = 0x07
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AD9914_REG_CFR3L = 0x09
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AD9914_REG_CFR3H = 0x0b
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AD9914_REG_CFR4L = 0x0d
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AD9914_REG_CFR4H = 0x0f
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AD9914_REG_FTWL = 0x2d
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AD9914_REG_FTWH = 0x2f
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AD9914_REG_POW = 0x31
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AD9914_REG_ASF = 0x33
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AD9914_REG_USR0 = 0x6d
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AD9914_FUD = 0x80
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AD9914_GPIO = 0x81
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class DDSGroupAD9914(DDSGroup):
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"""Driver for AD9914 DDS chips. See ``DDSGroup`` for a description
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of the functionality."""
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kernel_invariants = DDSGroup.kernel_invariants.union({
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"pow_width", "rtio_period_mu", "sysclk_per_mu", "write_duration_mu", "dac_cal_duration_mu",
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"init_duration_mu", "init_sync_duration_mu", "program_duration_mu",
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"first_dds_bus_channel", "dds_channel_count", "continuous_phase_comp"
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})
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pow_width = 16
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def __init__(self, *args, first_dds_bus_channel, dds_bus_count, dds_channel_count, **kwargs):
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super().__init__(*args, **kwargs)
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self.first_dds_bus_channel = first_dds_bus_channel
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self.dds_bus_count = dds_bus_count
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self.dds_channel_count = dds_channel_count
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self.rtio_period_mu = int64(8)
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self.sysclk_per_mu = int32(self.sysclk * self.core.ref_period)
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self.write_duration_mu = 5 * self.rtio_period_mu
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self.dac_cal_duration_mu = 147000 * self.rtio_period_mu
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self.init_duration_mu = 8 * self.write_duration_mu + self.dac_cal_duration_mu
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self.init_sync_duration_mu = 16 * self.write_duration_mu + 2 * self.dac_cal_duration_mu
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self.program_duration_mu = 6 * self.write_duration_mu
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self.continuous_phase_comp = [0] * (self.dds_bus_count * self.dds_channel_count)
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@kernel
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def batch_duration_mu(self):
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return self.batch.count * (self.program_duration_mu +
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self.write_duration_mu) # + FUD time
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@kernel
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def write(self, bus_channel, addr, data):
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rtio_output(now_mu(), bus_channel, addr, data)
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delay_mu(self.write_duration_mu)
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@kernel
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def init(self, bus_channel, channel):
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delay_mu(-self.init_duration_mu)
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self.write(bus_channel, AD9914_GPIO, (1 << channel) << 1);
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self.write(bus_channel, AD9914_REG_CFR1H, 0x0000) # Enable cosine output
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self.write(bus_channel, AD9914_REG_CFR2L, 0x8900) # Enable matched latency
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self.write(bus_channel, AD9914_REG_CFR2H, 0x0080) # Enable profile mode
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self.write(bus_channel, AD9914_REG_ASF, 0x0fff) # Set amplitude to maximum
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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@kernel
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def init_sync(self, bus_channel, channel, sync_delay):
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delay_mu(-self.init_sync_duration_mu)
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self.write(bus_channel, AD9914_GPIO, (1 << channel) << 1)
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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self.write(bus_channel, AD9914_REG_CFR2L, 0x8b00) # Enable matched latency and sync_out
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self.write(bus_channel, AD9914_FUD, 0)
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# Set cal with sync and set sync_out and sync_in delay
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self.write(bus_channel, AD9914_REG_USR0, 0x0840 | (sync_delay & 0x3f))
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self.write(bus_channel, AD9914_FUD, 0)
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0105) # Enable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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delay_mu(self.dac_cal_duration_mu)
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self.write(bus_channel, AD9914_REG_CFR4H, 0x0005) # Disable DAC calibration
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self.write(bus_channel, AD9914_FUD, 0)
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self.write(bus_channel, AD9914_REG_CFR1H, 0x0000) # Enable cosine output
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self.write(bus_channel, AD9914_REG_CFR2H, 0x0080) # Enable profile mode
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self.write(bus_channel, AD9914_REG_ASF, 0x0fff) # Set amplitude to maximum
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self.write(bus_channel, AD9914_FUD, 0)
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@kernel
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def program(self, ref_time, bus_channel, channel, ftw, pow, phase_mode, amplitude):
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self.write(bus_channel, AD9914_GPIO, (1 << channel) << 1)
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self.write(bus_channel, AD9914_REG_FTWL, ftw & 0xffff)
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self.write(bus_channel, AD9914_REG_FTWH, (ftw >> 16) & 0xffff)
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# We need the RTIO fine timestamp clock to be phase-locked
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# to DDS SYSCLK, and divided by an integer self.sysclk_per_mu.
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dds_bus_index = bus_channel - self.first_dds_bus_channel
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phase_comp_index = dds_bus_index * self.dds_channel_count + channel
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if phase_mode == PHASE_MODE_CONTINUOUS:
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# Do not clear phase accumulator on FUD
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# Disable autoclear phase accumulator and enables OSK.
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self.write(bus_channel, AD9914_REG_CFR1L, 0x0108)
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pow += self.continuous_phase_comp[phase_comp_index]
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else:
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# Clear phase accumulator on FUD
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# Enable autoclear phase accumulator and enables OSK.
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self.write(bus_channel, AD9914_REG_CFR1L, 0x2108)
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fud_time = now_mu() + 2 * self.write_duration_mu
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pow -= int32((ref_time - fud_time) * self.sysclk_per_mu * ftw >> (32 - self.pow_width))
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if phase_mode == PHASE_MODE_TRACKING:
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pow += int32(ref_time * self.sysclk_per_mu * ftw >> (32 - self.pow_width))
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self.continuous_phase_comp[phase_comp_index] = pow
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self.write(bus_channel, AD9914_REG_POW, pow)
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self.write(bus_channel, AD9914_REG_ASF, amplitude)
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self.write(bus_channel, AD9914_FUD, 0)
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class DDSChannelAD9914(DDSChannel):
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"""Driver for AD9914 DDS chips. See ``DDSChannel`` for a description
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of the functionality."""
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@kernel
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def init_sync(self, sync_delay=0):
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"""Resets and initializes the DDS channel as well as configures
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the AD9914 DDS for synchronisation. The synchronisation procedure
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follows the steps outlined in the AN-1254 application note.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 10ms provides a good
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timing margin.
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:param sync_delay: integer from 0 to 0x3f that sets the value of
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SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits.
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"""
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self.core_dds.init_sync(self.bus_channel, self.channel, sync_delay)
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