forked from M-Labs/artiq
32 lines
796 B
Python
32 lines
796 B
Python
from migen.fhdl.std import *
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from migen.genlib.record import Record
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def create_rbus(fine_ts_bits, pads, output_only_pads):
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rbus = []
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for pad in pads:
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layout = [
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("o_stb", 1),
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("o_value", 2)
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]
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if fine_ts_bits:
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layout.append(("o_fine_ts", fine_ts_bits))
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if pad not in output_only_pads:
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layout += [
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("oe", 1),
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("i_stb", 1),
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("i_value", 1),
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("i_pileup", 1)
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]
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if fine_ts_bits:
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layout.append(("i_fine_ts", fine_ts_bits))
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rbus.append(Record(layout))
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return rbus
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def get_fine_ts_width(rbus):
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if hasattr(rbus[0], "o_fine_ts"):
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return flen(rbus[0].o_fine_ts)
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else:
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return 0
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