artiq/artiq/compiler
2016-02-25 01:44:05 +00:00
..
algorithms compiler: do not associate SSA values with iodelay even when inlining. 2015-12-25 15:02:33 +08:00
analyses analyses.domination: all blocks dominate themselves. 2016-01-18 21:33:14 +00:00
testbench compiler: only use colors in diagnostics on POSIX (fixes #272). 2016-02-22 11:27:45 +00:00
transforms Take alignment into account during attribute writeback (fixes #293). 2016-02-25 01:44:05 +00:00
validators validators.escape: cache_get result lives forever. 2016-01-10 14:43:21 +00:00
__init__.py compiler: pull in dependencies in more finely grained way (fixes #181). 2015-11-24 17:32:04 +08:00
asttyped.py transforms/inferencer: add support for user-defined context manager. 2016-01-05 00:11:03 +08:00
builtins.py Implement dumb 'with parallel' (#265). 2016-02-22 13:51:08 +00:00
embedding.py Add rtio_log() and make print() an RPC (#206). 2016-02-15 03:56:56 +00:00
iodelay.py compiler.iodelay: correctly fold max(0, [0, ]...). 2015-11-24 00:46:55 +08:00
ir.py Rename 'with parallel' to 'with interleave' (#265). 2016-02-22 13:24:43 +00:00
module.py transforms.llvm_ir_generator: implement instrumentation for attribute writeback. 2016-01-02 06:51:30 +08:00
prelude.py Implement dumb 'with parallel' (#265). 2016-02-22 13:51:08 +00:00
targets.py artiq_run: allow running LLVM IR/bitcode files, even with trivial RPCs. 2016-02-24 22:50:45 +00:00
types.py validators.escape: cache_get result lives forever. 2016-01-10 14:43:21 +00:00