forked from M-Labs/artiq
114 lines
4.5 KiB
Python
114 lines
4.5 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from targets.kc705 import BaseSoC
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from artiqlib import rtio, ad9858
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_tester_io = [
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("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
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("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
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"LPC:LA05_N LPC:LA15_N")),
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Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
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"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
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"LPC:LA17_CC_N")),
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Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
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"LPC:LA13_N")),
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Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
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Subsignal("fud_n", Pins("LPC:LA14_P")),
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Subsignal("wr_n", Pins("LPC:LA04_P")),
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Subsignal("rd_n", Pins("LPC:LA02_N")),
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Subsignal("rst_n", Pins("LPC:LA12_P")),
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IOStandard("LVTTL")),
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]
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._r_clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._r_clock_sel.storage,
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o_O=self.cd_rtio.clk)
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class ARTIQSoC(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
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**kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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fud = Signal()
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
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self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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rtio_ins + rtio_outs,
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output_only_pads=set(rtio_outs))
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self.submodules.rtio = rtio.RTIO(self.rtiophy,
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clk_freq=125000000,
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ififo_depth=512)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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self.comb += dds_pads.fud_n.eq(~fud)
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default_subtarget = ARTIQSoC
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