artiq/artiq/gateware/rtio/phy
2016-11-18 17:08:44 +01:00
..
__init__.py rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
dds.py rtio: do not reset DDS and SPI PHYs on RTIO reset (#503) 2016-07-09 10:07:19 +08:00
sawg.py Revert "phaser: cap phy data width to 64 temporarily" 2016-11-18 17:08:44 +01:00
spi.py rtio: do not reset DDS and SPI PHYs on RTIO reset (#503) 2016-07-09 10:07:19 +08:00
ttl_serdes_7series.py rtio: add input-only channel 2016-10-05 16:17:50 +02:00
ttl_serdes_generic.py rtio/phy/ttl: support 'set sensitivity and sample' command (#218) 2016-09-07 15:42:09 +08:00
ttl_serdes_spartan6.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
ttl_simple.py ttl_simple: add pure Input 2016-10-10 17:13:23 +02:00
wishbone.py rtio: remove NOP suppression capability 2016-03-10 09:47:29 +08:00