forked from M-Labs/artiq
58 lines
3.5 KiB
Python
58 lines
3.5 KiB
Python
"""
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The traditional RTIO system used one dedicated FIFO per output channel. While this architecture
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is simple and appropriate for ARTIQ systems that were rather small and simple, it shows limitations
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on more complex ones. By decreasing importance:
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* with DRTIO, the master needed to keep track, for each FIFO in each satellite, a lower bound on
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the number of available entries plus the last timestamp written. The timestamp is stored in order
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to detect sequence errors rapidly (and allow precise exceptions without compromising performance).
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When many satellites are involved, especially with DRTIO switches, the storage requirements become
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prohibitive.
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* with many channels in one device, the large muxes and the error detection logic that
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can handle all the FIFOs make timing closure problematic.
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* with many channels in one device, the FIFOs waste FPGA space, as they are never all filled at the
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same time.
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The scalable event dispatcher (SED) addresses those issues:
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* only one lower bound on the available entries needs to be stored per satellite device for flow
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control purposes (called "buffer space"). Most sequence errors no longer exist (non-increasing
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timestamps into one channel are permitted to an extent) so rapid detection of them is no longer
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required.
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* the events can be demultiplexed to the different channels using pipeline stages that ease timing.
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* only a few FIFOs are required and they are shared between the channels.
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The SED core contains a configurable number of FIFOs that hold the usual information about RTIO
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events (timestamp, address, data), the channel number, and a sequence number. The sequence number is
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increased for each event submitted.
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When an event is submitted, it is written into the current FIFO if its timestamp is strictly
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increasing. Otherwise, the current FIFO number is incremented by one (and wraps around, if the
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current FIFO was the last) and the event is written there, unless that FIFO already contains an
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event with a greater timestamp. In that case, an asynchronous error is reported. If the destination
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FIFO is full, the submitter is blocked.
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In order to help spreading events among FIFOs and maximize buffering, the SED core may optionally
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also switch to the next FIFO after the current FIFO has been full.
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At the output of the FIFOs, the events are distributed to the channels and simultaneous events on
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the same channel are handled using a structure similar to a odd-even merge-sort network that sorts
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by channel. When there are simultaneous events on the same channel, the event with the highest
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sequence number is kept and a flag is raised to indicate that a replacement occured on that
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channel. If a replacement was made on a channel that has replacements disabled, the final
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event is dropped and a collision error is reported asynchronously.
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Underflow errors are detected as before by comparing the event timestamp with the current value of
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the counter, and dropping events that do not have enough time to make it through the system.
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The sequence number is sized to be able to represent the combined capacity of all FIFOs, plus
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2 bits that allow the detection of wrap-arounds.
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The maximum number of simultaneous events (on different channels), and the maximum number of active
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timeline "rewinds", are equal to the number of FIFOs.
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The SED logic support both synchronous and asynchronous FIFOs, which are used respectively for local
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RTIO and DRTIO.
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To implement flow control in DRTIO, the master queries the satellite for buffer space. The satellite
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uses as buffer space the space available in its fullest FIFO.
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"""
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