forked from M-Labs/artiq
256 lines
9.0 KiB
Python
256 lines
9.0 KiB
Python
from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFO
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from artiqlib.rtio.rbus import get_fine_ts_width
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal()
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self.replace = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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# # #
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# detect underflows
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self.sync += \
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If((self.we & self.writable) | self.replace,
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If(self.timestamp[fine_ts_width:] < counter + 2,
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self.underflow.eq(1))
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)
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fifos = []
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for n, chif in enumerate(rbus):
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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2 if chif.mini else fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO replace/write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq((self.we | self.replace) & (self.sel == n)),
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fifo.replace.eq(self.replace)
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]
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# FIFO read
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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]
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if fine_ts_width:
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self.comb += chif.o_fine_ts.eq(
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fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += [
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self.writable.eq(selfifo.writable),
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self.level.eq(selfifo.level)
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]
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class _RTIOBankI(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal()
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal()
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self.pileup_count = Signal(16)
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self.pileup_reset = Signal()
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# # #
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timestamps = []
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values = []
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readables = []
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overflows = []
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pileup_counts = []
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for n, chif in enumerate(rbus):
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if hasattr(chif, "oe"):
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sensitivity = Signal(2)
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self.sync += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 1)],
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fifo_depth)
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self.submodules += fifo
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# FIFO write
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if fine_ts_width:
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full_ts = Cat(chif.i_fine_ts, counter)
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else:
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full_ts = counter
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self.comb += [
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fifo.din.timestamp.eq(full_ts),
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fifo.din.value.eq(chif.i_value),
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fifo.we.eq(
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~chif.oe & chif.i_stb &
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((chif.i_value & sensitivity[0])
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| (~chif.i_value & sensitivity[1])))
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]
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# FIFO read
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timestamps.append(fifo.dout.timestamp)
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values.append(fifo.dout.value)
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readables.append(fifo.readable)
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self.comb += fifo.re.eq(self.re & (self.sel == n))
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overflow = Signal()
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self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
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overflows.append(overflow)
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pileup_count = Signal(16)
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self.sync += \
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If(self.pileup_reset & (self.sel == n),
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pileup_count.eq(0)
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).Elif(chif.i_pileup,
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If(pileup_count != 2**16 - 1, # saturate
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pileup_count.eq(pileup_count + 1)
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)
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)
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pileup_counts.append(pileup_count)
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else:
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timestamps.append(0)
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values.append(0)
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readables.append(0)
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overflows.append(0)
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pileup_counts.append(0)
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self.comb += [
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self.timestamp.eq(Array(timestamps)[self.sel]),
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self.value.eq(Array(values)[self.sel]),
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self.readable.eq(Array(readables)[self.sel]),
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self.overflow.eq(Array(overflows)[self.sel]),
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self.pileup_count.eq(Array(pileup_counts)[self.sel])
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]
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=64):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Counters
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reset_counter = Signal()
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o_counter = Signal(counter_width, reset=phy.loopback_latency)
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i_counter = Signal(counter_width)
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self.sync += \
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If(reset_counter,
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o_counter.eq(o_counter.reset),
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i_counter.eq(i_counter.reset)
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).Else(
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o_counter.eq(o_counter + 1),
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i_counter.eq(i_counter + 1)
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)
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# Submodules
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self.submodules.bank_o = InsertReset(_RTIOBankO(
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phy.rbus,
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o_counter, fine_ts_width, ofifo_depth))
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self.submodules.bank_i = InsertReset(_RTIOBankI(
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phy.rbus,
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i_counter, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset_logic = CSRStorage(reset=1)
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self._r_reset_counter = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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self._r_o_value = CSRStorage(2)
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_replace = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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self._r_i_timestamp = CSRStatus(counter_width+fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_readable = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_overflow = CSRStatus()
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self._r_i_pileup_count = CSRStatus(16)
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self._r_i_pileup_reset = CSR()
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter_update = CSR()
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self._r_frequency_i = CSRStatus(32)
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self._r_frequency_fn = CSRStatus(8)
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self._r_frequency_fd = CSRStatus(8)
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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if hasattr(chif, "oe"):
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self.sync += \
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If(self._r_oe.re & (self._r_chan_sel.storage == n),
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chif.oe.eq(self._r_oe.r)
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)
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oes.append(chif.oe)
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else:
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oes.append(1)
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self.comb += self._r_oe.w.eq(Array(oes)[self._r_chan_sel.storage])
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset_logic.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self.bank_o.replace.eq(self._r_o_replace.re),
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self._r_o_underflow.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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# Input
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self.comb += [
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self.bank_i.reset.eq(self._r_reset_logic.storage),
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self.bank_i.sel.eq(self._r_chan_sel.storage),
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self._r_i_timestamp.status.eq(self.bank_i.timestamp),
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self._r_i_value.status.eq(self.bank_i.value),
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self._r_i_readable.status.eq(self.bank_i.readable),
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self.bank_i.re.eq(self._r_i_re.re),
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self._r_i_overflow.status.eq(self.bank_i.overflow),
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self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
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self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
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]
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# Counter access
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self.comb += reset_counter.eq(self._r_reset_counter.storage)
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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o_counter))
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)
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# Frequency
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clk_freq = Fraction(clk_freq).limit_denominator(255)
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clk_freq_i = int(clk_freq)
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clk_freq_f = clk_freq - clk_freq_i
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self.comb += [
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self._r_frequency_i.status.eq(clk_freq_i),
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self._r_frequency_fn.status.eq(clk_freq_f.numerator),
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self._r_frequency_fd.status.eq(clk_freq_f.denominator)
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]
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